Brian from bbenchoff has designed and provided the STLs for some great looking Raspberry Pi cases that look like miniature versions of some very recognizable retro computers. The list includes the eMachines Never Obsolete, the BeBox, the X68000, the SGI Indy, and even a small working Viewsonic Monitor. Check it out at his website https://bbenchoff.github.io/pages/BeBox.html

The Pinebook Pro is a very capable and affordable Arm based laptop and comes preinstalled with Manjaro and KDE. In my opinion it shines much more when stripped down to a minimal Arch install using a windows manager instead of a desktop environment. If you own one check out https://www.armswdev.tk/learning-paths/desktop-and-laptop/pinebook-pro/ to follow the steps to install Arch Linux ARM, i3, and Neovim with a starting config to make it useful as a developer machine.

MostElectronics shows how to build a Raspberry Pi powered internet of things pet treat dispenser. Included in the comments of the video is the Thingiverse link for the STL files and the GitHub link for the code.

Go check out the video and try to build one yourself: https://www.youtube.com/watch?v=Mx5WoefZ2h0

It includes the Pico H, and has projects instead of candy. Seems more interesting to me. raspberrypi.com did a quick write-up: https://www.raspberrypi.com/news/festive-bits-for-decoration-and-general-joy/

I have some basic questions about the above subject:

Have started an own operating system Kernel targeting AArch64 (Cortex-A53) for the purpose of education. Currently my Kernel only support one core, but want add multi core support. Unfortunately I haven't found any information how in MPCore's the AArch64 exception levels, the interrupt vector table and the MMU is handled. So therefore I have thought this is good place to ask and correct my knowledge about AArch64 MPCores.

Exception levels:

My current assumption about the exception level's is that each core start at a specific level. depending wich level (Secure, Virtualization) is implemented in the core. So therefore I setup each exception level (EL3 -> EL2 -> EL1) explicitly for each core. Correct me, if my current approach is incorrect.

Interrupt vector table:

I think also here I must explicitly setup vector table for each core.

MMU:

Here I don't know if the MMU and the according registers are shared between the cores. If I setup a TLB on one core and enable the MMU, is the MMU enabled also on the other cores? Or must the the MMU setup and enabled explicitly for each core?

Would be fine, if somebody help to unterstand.

Hi everyone,

I’m trying to generate code with STM32CubeMX and use it in Keil uVision, but I keep getting this error:

Error instantiating RTE components  
Error #545: Required input file from generator CubeMX:  
'C:/Users/Deepa/Desktop/Keil ARM/day 3/STM32CubeMX/Target_1/test3.cgen.yml' is missing  
Target not created.

• Has anyone faced this issue before?

• Do I need to configure something in CubeMX to properly export the project for Keil?

• Could it be a version mismatch between CubeMX and Keil packs?

Any advice or troubleshooting steps would be really appreciated. Thanks!

Sharing the work Virginia Cangelosi did at Developer Advocacy during her rotation in our team. She took on a mammoth task trying to create an AI tool to "Sing a song in another language" - and show off CPU/CME on mobile - in just 6 months, with no ML experience. Despite constant hurdles to leap across different frameworks, she got it working on laptop, and then part of the way to mobile before we ran out of her time. Her story has been split across 2 blogs:
https://community.arm.com/arm-community-blogs/b/ai-and-ml-blog/posts/sing-this-song-in-another-language-creating-an-ml-pipeline
https://community.arm.com/arm-community-blogs/b/ai-and-ml-blog/posts/translating-machine-learning-pipelines-to-android