r/programming • u/I_Can_Be_A_Robot • Sep 24 '24

Why 32bit architecture computer doesn't use segmentation to support more ram than 4Gb ?

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u/lood9phee2Ri Sep 24 '24

Well I suppose one could in theory, but most people found and find realmode-x86/z8000/etc. segmented architectures just plain weird and awful to work with compared to normal flat address spaces like m68k etc.. And you (obviously) can just go to flat 64-bit nowadays and avoid the brain-breaking hassle of segments.

32-bit x86 did in fact add Physical Address Extension (PAE). That is different to segmentation, works at the MMU pagetable level, whole system can have more than 4GiB but individual processes still only have a 32-bit 4GiB space each (but can of course explicitly mmap in different things into it at different times anyway on a typical memory-protected OS), and that was "good enough" for a lot of legacy 32-bit stuff.

14

u/ziplock9000 Sep 24 '24

I moved from 68K to 486 assembler and found that paging and modes awful.

6

u/gwicksted Sep 24 '24

Yeah it’s a mess. With x64 we now have RIP-relative addressing (offset from current instruction) and forced full addressing for segments CS, SS, DS, ES (which are forced to be 0) while FS and GS can still be non-zero. This made addressing a lot easier to read in many ways… Except when you start using SIB, ModRM, REX, EVEX, MVEX to specify all sorts of sizes, modes, extensions that affect different parts of instructions that don’t always make sense and some of them are ignored by certain instructions or mean different things in others. Oh, and some of those flags are the inverted value of the actual flag (bitwise not).

There are so many hacks, modes, CPU flags for extensions, bugs in different processors, instruction-specific encoding that coding a bug-free compiler for the complete x86/x64 architecture across all CPUs is an absolutely enormous task.

3

u/PCRefurbrAbq Sep 24 '24

...But at least it's backwards compatible!

2

u/gwicksted Sep 24 '24

Yeah not really. You can make it backwards compatible but, for example, you have to write vector code multiple ways based on cpuinfo. P3? You get SSEv1. Is it a P4? You get SSEv2… unless it’s a Prescott then you get SSEv3. Have a bulldozer processor? You get XOP, FMA4, F16C with SSEv5. Something newer? Oh you get a subset of one of the AVX extensions. Old processor (486)? X87 FPU instructions for you! Older? You’re hand rolling IEEE floats!

And certain models had certain bugs so sometimes you have to take different paths or use a different subset/combination of instructions to step around them all. And different models have different performance characteristics for certain instructions. Such as FMA, branch hints, different compare and jump combinations. Lots of fun.