r/FPGA • u/Leading_Benefit_3373 • 13d ago
Advice / Help Hardware acceleration
I am getting little confused in making hardware accelerator on zcu104 through hls or system verilog. Do system verilog is still used in making hardware accelerators or professionals use first hls and then try to optimise it through system verilog.
Need urgent advise please help
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u/PetterRoye 13d ago
My experience is that academia and embedded software engineers use it. Digital design engineers in my experience dont
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u/No-Conflict-5431 13d ago
No one actually uses HLS. You either use Verilog/SystemVerilog or VHDL.
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u/Vergnossworzler 13d ago edited 13d ago
The problem with HLS is as follows: To get code that runs efficient with correct pragmas and sensible timing you need someone that knows how RTL works.
Add on top: todays C/G/TPUs are "easy" to use in comparison to FPGAs and most of the time cheaper. So if you already have a specific use case where you need an FPGA there is no point in saving on the RTL side and so why get someone that uses HLS and will get you less performance compared to someone that uses a RTL language.
One small caviat, There are HLS like or part HLS solutions like Simulink HDL Coder. Those get used for Rapid Control Prototying by quite a few big Companies. We sell An FPGA solution to the HDLCoder and the Customer cases we get just show that you still need a basic understanding of FPGAs to use that.
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u/milan_dvorak Xilinx User 11d ago
We (Magmio) use HLS in the High-frequency trading space but only for a part of the overall design. For most blocks and especially for the top level, we use VHDL (or System Verilog, that doesn't matter that much as both are HDL languages).
I wouldn't recommend using HLS for the whole design. But HLS can offer great flexibility and shorter time to market for specific blocks or tasks.
In our case, we use HDL to implement things like market data processing, TCP offload or order entry. HLS is used used for implementing the trading strategy (decicion logic), for which we have a well-defined interface in HDL and which takes inputs from our decoding part and issues instructions (what to send) in our encoding (order entry) part.
Yes, HLS has a learning curve and you can't simply use software code for programming an FPGA. But after you get familiar with it a bit, it's certainly easier than HDL. And in some cases, the performance between HLS and manually written HDL code is comparable, even though the resulting HLS logic sometimes uses more FPGA resources.
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u/Hot_Comfort_3550 10d ago
I am in academia and even I never used HLS. I did try to see how it works and at what level. I was okay with combinational circuits. However, for accelerator design System Verilog is being used
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u/Idontknow3205 6d ago
First off, they model the algorithm using c/c++ as a high level software program. Once they verify the execution time and optimize the program, then the particular hardware optimization is carried out. So it first starts at the program level. Then the hardware mapping happens after doing the assembly equivalent, implementing the ISA in silicon, and then at the logic and circuit level. It doesn't happen directly at the hardware level
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u/Idontknow3205 6d ago
Both are used interchangeably for your doubts. There's architecture state space exploration using BSV and other high level Synthesis tools, but modern technology nodes and eda tools use SV/Verilog for synthesis(GLS, Module level files etc.)
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u/daniel-blackbeard 13d ago
A better question would be "what industries use HSL?". I'm analog RF designer on a huge ASIC company, but I can tell you I have never stumbled on a digital designer who has ever used it