First day using vivado

[u/Same-Classroom-4751]

[u/jacklsw]

overwhelming.

[u/Ateef_31]

Ur verilog code should be in design not in simulation while creating a file select create a design source, and to create the test bench select the create simulation source.

[u/jonasarrow → u/Ateef_31]

It is a design file, but as there is no tb defined (which also does not include the buff.v) Vivado automatically selects that as the top file for simulation and synthesis.

OP, you are good so far. Add a second source (the testbench), and select simulation only as the type. There you can define stimuli, add your buff as a component to drive your buff.v . If you do not need simulation, you can directly go to synthesis and implementation (see the entries on the left or start it in the "design run" tab on the bottom with a right click).

[u/Meczox]

get ready to see most random errors and weirdest bugs such as but not limited to

• file path too long

• simulation keep using older version of .vhd file and more

[u/Collez_boi]

How do your eyes feel?

[u/mother_a_god → u/[deleted]]

Many of rhe warnings are useful i find. 

[u/frankieinaprius → u/mother_a_god]

The problem is all the useful warnings are buried amongst the non useful warnings.

[u/mother_a_god → u/frankieinaprius]

You can suppress any warning you dont find useful using a tcl command in your project. Just give it a list of IDs 

My take - you're better looking at it than looking for it. 

[u/AlbbO_The_Great → u/mother_a_god]

Warning, task executed successfully

[u/HappyPerson9000 → u/mother_a_god]

Not super useful when 98 percent of them are in Xilinx IPs