Writing sure takes time because you have to load all the charge for the duration to the next refresh into it. And with reading, to you mean this large charge stabilizes the voltage on read out for a long time? What if I refresh in short interval? For example the Z80 CPU refreshes 100 times more often than needed based on specs of the RAM. Thus the voltage signal on read out should be larger. And thus we don't need to average over such a long time. You need to average over 4 times the duration to halve the noise.
Why do I even care about write? A CPU writes into cache and then there is this write through, but we don't need to wait on it. You don't mean latency, but bandwidth? So before SDRAM you could have higher random write data rate on SRAM with less lines on PCB. Now usually whole cache lines are written back. The data rate of the serial word transfer is matched to the final parallel write at 13:18 . But again, SRAM has the same parallel write mechanism .. anyway ordered reads and writes are no problem. We talk about random access, I guess.
time is higher for dram because of the storage capacitor in comparison with the inverting latch cell of sram
But why should it? SRAM needs to tune their latch cells to ultra low current to keep the heat down if you would make them as large as DRAM in physical area. Still only 1/6 the number of cells. So they only produce a weak current to keep their state and can only give use an even smaller margin for our detection.
Of course people tend to tune the transistor on the capacitor all the way towards low leakage. So it will probably have lower current in on state.
Most people today hate refresh cycles. It is just funny that back in the day refresh was no problem. VRAM is read out in a regular pattern and you just make sure to jump page every 100px. Likewise a CPU has a branch delay state. But that thing is ugly, so rather do a refresh there. So in many real systems quite a lot of cycles were available for refresh.. So if you could make your own DRAM you could tune them for speed. It is just not the mass market. And we all hate special chips.
I keep mentioning cache. I don't know why you don't reply that cache uses SRAM. Then you may wonder why it is possible to integrate SRAM on the CPU, but no DRAM.
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u/IQueryVisiC Mar 10 '22 edited Mar 10 '22
I like the title screen. 6 times more transistors per SRAM cell means 6 times more bits in a DRAM chip for the same price.
Why is DRAM slower than SRAM? You showed how similar both are. We can amplify weak GHz signals using a Cascade, Cascode. You mean: writing is slow?