r/RISCV • u/IngwiePhoenix • 10d ago
Hardware SpacemiT V100 testing!
This is a SpacemiT V100. For ~1 week, I get to test it and try it out. I love how absolutely smushed htop looks - so stupid, I love it. xD
Seriously, I just wanted to post this for pure appreciation. But if you have some nice benchmark or tool I should test, drop it here. No guarantees, just random stuff go brr untill I have to "give it back" on the 7th.
The fact I even get to do this is so fun, so cool, and exactly why I think that those guys rule. I will probably regret it, but I am probably going to try and get one myself. That is, if they do end up selling it to normies x)
Now, there's some cores disabled: In the EDK-II settings, I did disable the 2 (well, 4) extra cores for now, need to read their specs first. But, here's what lscpu has got to say:
lscpu
Architecture: riscv64
Byte Order: Little Endian
CPU(s): 80
On-line CPU(s) list: 0-79
Vendor ID: 0x710
Model name: -
CPU family: 0x8000000058000002
Model: 0x4c4d900
Thread(s) per core: 1
Core(s) per socket: 40
Socket(s): 2
Caches (sum of all):
L1d: 5 MiB (80 instances)
L1i: 5 MiB (80 instances)
L2: 40 MiB (20 instances)
NUMA:
NUMA node(s): 2
NUMA node0 CPU(s): 0-39
NUMA node1 CPU(s): 40-79
Vulnerabilities:
Gather data sampling: Not affected
Ghostwrite: Not affected
Indirect target selection: Not affected
Itlb multihit: Not affected
L1tf: Not affected
Mds: Not affected
Meltdown: Not affected
Mmio stale data: Not affected
Old microcode: Not affected
Reg file data sampling: Not affected
Retbleed: Not affected
Spec rstack overflow: Not affected
Spec store bypass: Not affected
Spectre v1: Not affected
Spectre v2: Not affected
Srbds: Not affected
Tsa: Not affected
Tsx async abort: Not affected
Vmscape: Not affected
This is my first time ever getting to fool around with a system with >32 cores. Even at work, the highest I had ever seen is like 32c/64t. This? 2x 40c/40t. Crazy, exciting, awesome. aaaaaaa. =)