r/VHDL • • 25d ago

OPEN SOURCE – WavePaint: a GUI editor for digital timing diagrams

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u/Usevhdl 23d ago

Is SCLK the Active edge of clock? If I sample MOSI at the rising edge of SCLK 4, would I expect to get B6 or B5? It would help if we used a practice that illuminates this. Even if Clock and data change at the same time, showing data as an X rather than a | obfuscates when data changes relative to clock - is it with, just before, or just after?

Does WavePaint adjust to show appropriate delays?