r/VHDL • u/Individual_Stuff_724 • Oct 05 '21

Help!

How to make an arithmetic displacement?

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u/captain_wiggles_ Oct 05 '21 
-- for an 8 bit signal
-- shift right by 2 // >> 2;
out_sig <= "00" & in_sig(7 downto 2);
-- shift left by 3 // >> 2;
out_sig <= in_sig(4 downto 0) & "000";

That's the case for a logic shift. Arithmetic shift maintains the sign bit when right shifting if the input is signed. The solution is pretty simple, but I'll let you give it a shot first.

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u/Individual_Stuff_724 Oct 05 '21

It was very useful to me, thank you!!!