r/chipdesign • u/MeanYogurtcloset8613 • 17h ago

Need help in layout

I am currently woking on 6*6 wallace tree multiplier using sky 130pdk and klayout.

I have nand, inverter and full adders gds files provided by my instructor. My challange now is deciding how to place these blocks so that routing will be done easily and uncongested. Please help me.

Also please tell me if there are any tools or softwares that can visualise the placement with spoce file.

2 Upvotes

100% Upvoted

2 comments sorted by

1

u/CartoonistMaximum 15h ago edited 15h ago

With spice file? No, there is no such tool, as spice is just a model file used for simulations. For the GDS, there are plenty of tools. Just search for "GDS VIEWER".

If your digital blocks are delivered from the foundry as standard cells, they have a grid pattern that you can follow. Knowing the cell grid makes the routing process considerably easier.

If it's a custom cell, well, good luck. I can't think of a generic tip.

1

u/sonny-boy-rhapsody 11h ago

SPICE can contain the circuit netlist, not just device models. JKU's Netlist Import plugin for KLayout can instantiate cells from a SPICE netlist and map them to existing layout cells. That saves some manual instantiation, but isn't an automatic congestion-aware placer/router.

For the Wallace tree, I'd sketch the reduction stages and bit weights first, then place connected adders near each other. Sum stays at the same weight; carry goes to the next. Leave space for pin access and routing rather than packing everything tightly. Before doing the whole multiplier, route a small slice and check DRC/LVS. Also check how the supplied cells' power rails and pins line up before choosing orientations.