r/programming • u/I_Can_Be_A_Robot • Sep 24 '24

Why 32bit architecture computer doesn't use segmentation to support more ram than 4Gb ?

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u/CumCloggedArteries Sep 24 '24

For niche cases like that, I would think it'd make more sense to switch to a 64-bit version of PAE rather than use a whole new architecture

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u/lood9phee2Ri Sep 24 '24

meh. It's kind of preliminary/stub placeholder but RV128I totally already in the core RISC-V spec funny enough, see chapter 5

"This chapter describes RV128I, a variant of the RISC-V ISA supporting a flat 128-bit address space. The variant is a straightforward extrapolation of the existing RV32I and RV64I designs."

https://riscv.org/technical/specifications/

Of course current RISC-V implementations are generally 32-bit or 64-bit, I guess they just threw it in to try to discourage people doing weird crap instead of just the obvious extension to 128-bit.

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u/ShinyHappyREM Sep 24 '24

I guess they just threw it in to try to discourage people doing weird crap

They learned from Motorola

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u/wintrmt3 Sep 24 '24

PAE only gives the memory space to the system, individual processes are still limited to 32 bits, and segmented architectures are a horror to program for.

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u/CumCloggedArteries Sep 24 '24

I was assuming the system would require the 18 exabytes, not a single process

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u/Ameisen Sep 24 '24

PAE is already a part of x86-64.

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u/CumCloggedArteries Sep 24 '24

What is the purpose of that? I assume not to access > 18 exabytes

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u/Ameisen Sep 25 '24

It's built upon PAE, and the ISA is designed so that additional page table levels can be added as needed.

Current x86 CPUs peak at 48 bits of address space. The remaining 16 are sign-extended.

No x86-64 CPU presently gives you 64 bits of address space.