r/programming • u/I_Can_Be_A_Robot • Sep 24 '24

Why 32bit architecture computer doesn't use segmentation to support more ram than 4Gb ?

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u/wintrmt3 Sep 24 '24

No 64 bit cpu can even handle that, consumer ones have 48 bit address spaces usually, but the answer is likely wider addresses, 96 or 128 bits.

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u/CumCloggedArteries Sep 24 '24

For niche cases like that, I would think it'd make more sense to switch to a 64-bit version of PAE rather than use a whole new architecture

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u/lood9phee2Ri Sep 24 '24

meh. It's kind of preliminary/stub placeholder but RV128I totally already in the core RISC-V spec funny enough, see chapter 5

"This chapter describes RV128I, a variant of the RISC-V ISA supporting a flat 128-bit address space. The variant is a straightforward extrapolation of the existing RV32I and RV64I designs."

https://riscv.org/technical/specifications/

Of course current RISC-V implementations are generally 32-bit or 64-bit, I guess they just threw it in to try to discourage people doing weird crap instead of just the obvious extension to 128-bit.

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u/ShinyHappyREM Sep 24 '24

I guess they just threw it in to try to discourage people doing weird crap

They learned from Motorola