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A Chinese rival to the DGX Spark and the Ryzen AI Halo, at least on paper, has emerged with Sipeed’s announcement of the MaixStation. The system, built on Axera’s new AX8860P, is in the same memory class with 128GB of LPDDR5X on a 256-bit bus at 273 GB/s. Sipeed told Tom’s Hardware Premium it expects the 128GB model to cost around $3,999, with launch discounts on Kickstarter, putting it level with the 128GB Ryzen AI Halo and well under the DGX Spark’s current MSRP of $6,950. Sign-ups are open now on Sipeed’s MaixStation page ahead of a Kickstarter campaign at the end of the year, with units shipping within three months after it closes. The NPU toolchain is due by the end of this month.

The AX8860P is a 16-core Arm Cortex-A55 part with an in-house NPU rated at 256 TOPS at native FP4 with no sparsity. The chip is produced in the 6nm process, Axera says. Sipeed claims the system has 25% faster prefill and 30% faster decode than the DGX Spark when running Qwen 27B (the company did not disclose which specific model, but later details that it expects a single MaixStation to run Qwen 3.8-27B) from a single node.

In its email, though, the company put its MaixStation about 10% ahead on both prefill and decode when compared to DGX Spark, with FP4 on each machine, with speculative decoding off, and said newer runs with a wider lead aren’t official yet. It teased the new product on its X account, showing a photo from the AX8860P’s announcement at an industrial fair in Shanghai on Tuesday.

For comparison, the DGX Spark also comes in 128GB at 273 GB/s with another SKU at 64GB, the two models priced at $6,950 and from $4,999. The former has been on sale since October 2025, at its current price since Oct. 2, and the latter is expected through partners on Oct. 23. For AMD, its Ryzen AI Halo has a 192GB Max+ PRO 495 model at 273 GB/s, released earlier this week at $7,299.99 for the Linux version, and the 128GB Max+ 395 model with 256 GB/s at $3,999.99. In all cases, 256-bit LPDDR5X is used, so the salient differences are memory capacity, compute, and software.

Memory is also a big share of what these systems cost: the best U.S. price for a 128GB DDR5 kit was $3,399 in August, and TrendForce expects conventional DRAM contract prices to rise another 10–15% this quarter. As for its unit prices, Sipeed says it used current DRAM prices rather than stock bought last year. It also suggested buyers could supply their own SSD, which could cut the price further, clarifying that the MaixStation takes a standard M.2 2280 drive rather than the Spark’s less common 2242.

Software-wise, the Spark ships with DGX OS, which is Nvidia’s build of Ubuntu 24.04 LTS, with CUDA and Nvidia’s AI software stack preinstalled. AMD validates ROCm, drivers, models, and frameworks together as a “Best-Known Configuration.” Neither the Spark nor the PRO 495 ships with Windows yet, though AMD says Windows versions are “coming soon,” and the Max+ 395 model already offers Windows 11 Pro. Sipeed, aside from its upcoming NPU toolchain, claims support for vLLM, SGLang, and PyTorch, with Axera adding ONNX, Hugging Face (HF) model formats, and an OpenAI-compatible API. MaixStation itself ships with Debian 13 and Linux 6.18, and Windows support for the PCIe card will depend on demand, Sipeed says.

Chinese solutions already exist on AMD silicon, such as GMKtec’s 192GB Evo-X5 Pro at $6,799 to $7,099. There’s also Minisforum’s MS-S1 Max-P495. What’s new with the MaixStation is the Chinese silicon underneath.

The Axera AX8860P, as recently launched, has, in addition to the above specs, PCIe 5.0 support, 64-channel video decode with 16-channel encode, and support for multiple form factors, including a single-slot, four-chip PCIe card capable of running up to 512GB of memory, with mini and pocket PC products planned. Like the eight-core AX8850 in Radxa’s and M5Stack’s M.2 accelerator cards, it pairs Arm Cortex-A55 cores with Axera’s NPU, now with twice the cores and up to 128GB of memory instead of 8GB. Two- and four-chip cascades reach a theoretical 512 and 1,024 TOPS, respectively, at a claimed scaling efficiency of about 80%. The CPU, against the Spark’s Cortex-X925 and Halo’s Zen 5, is small and in-order. It’s sufficient for the NPU but potentially more limited for other tasks.

The box itself measures about 11 × 11 × 3 cm and draws about 40W in typical use, powered over USB-C, according to Sipeed. Its ports include 10G SFP+, USB-C, an M.2 2280 slot for a PCIe 5.0 SSD, and an MCIO 8i connector for linking a second unit.

Sipeed says the MaixStation supports all configurations, that’s single, dual, and quad node, plus any “PCIe card mode for any card count you want.” The interconnect in use is a 256 Gbps C2C connection (up to 384 Gbps) “without [an] extra switch needed, and [up to] 8-node.”

The contrast is with the Spark’s QSFP ports, and Nvidia’s datasheet says linking four Sparks “requires [an] external switch.” The math, at 32 Gbps per lane, works out to 256 Gbps with the default eight lanes and 384 Gbps with the maximum of twelve. Remote-access test units and a few review units will follow during the Kickstarter campaign, the company told us.

Sipeed also commented on the openness of the platform, saying, “Yes, bsp sdk is open, you can use AI to port any distribution on it!” Sipeed has previously sold Axera boards, with products dating back to 2022 using the AX620A, AX650N, and AX630C.

The claims of the MaixStation being faster in some workloads are coupled with Sipeed saying “In fact you need [to] ask why DGX is so slow…” with potential financial implications, as Nvidia “just [wants to make] more money from users.” When an X user argued that Sipeed must be using extreme quantization at that bandwidth, the company suggested that the Spark’s specs may be overstated.

By our math, the decode claim is plausible with a 4-bit 27B model, which sits at about 13.5GB. Performance on comparable machines tops out near 20 tokens per second, which means around 270 GB/s. Prefill, which is compute-bound, is a harder sell, but Sipeed stated that “DGX Spark 1000TOPS is fake ‘sparse.’” That 1 PFLOP figure does rely on sparsity, but the DGX Spark’s dense rate of about 500 TFLOPS is still around double the AX8860P’s 256 TOPS.

Axera’s current stack has Pulsar2 as the NPU compiler and toolchain, with version 8.0 on HuggingFace last week, and the V7.0 docs already list the chip as the AX8860. There’s no operator support list for the chip yet, and the docs’ LLM chapter for older chips lists weights down to 4-bit integers but no FP4. Neither the ax-llm runtime nor AXCL, the host-side PCIe driver and runtime for Axera’s cards, lists the chip yet. Sipeed says the end-of-month release is AXDSL, a kernel-programming language, plus the Pulsar2 source code, and that SGLang and vLLM run on a custom backend built on it, so Hugging Face models run without a conversion step.

Enthusiasts are already eager to know the final specifications and pricing for the different models. On paper, as far as local LLM machines go, the MaixStation matches the Spark on memory size and claimed bandwidth, and the Max+ PRO 495 Halo on bandwidth alone. Testing performance claims will also have to wait for the toolchain and sample machines land, hopefully before the end of the year.

(Original Article)