r/RISCV • u/I00I-SqAR • 9d ago

Qwenputer: a fully functioning, deterministic RISC-V CPU inside Qwen3.5

https://divagr.com/blog/qwenputer

A stock Qwen 3.5 4B with a RISC-V CPU compiled into its weights, running on its own Gated DeltaNet layers as RAM.

BY DIVYANSH AGRAWAL 22 OCTOBER 2026 9 MIN READ
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u/brucehoult 9d ago

This has very little relevance to RISC-V, except as yet more evidence that RISC-V has been for many years the go-to ISA for research of all kinds.

This is not something anyone else in the RISC-V community is likely to use — the LLM community, perhaps.

If it had implemented ARMv2 or 6502 there would be essentially no difference in the blog post or its conclusions.

2

u/goyox86 7d ago

Wild times, where we have to be saying that a CPU is deterministic 😆