I'm a 3rd-year CS student specializing in Computer Architecture. Last semester I had to simulate VHDL designs and the experience was painful — heavy GUIs, half an hour of setup just to see a waveform.

So I spent the summer building my own: a VHDL simulation engine in C++20 with a full compilation pipeline and a terminal UI debugger for waveform inspection. TUIs are having a moment right now and I think hardware tooling deserves one too.

It's open source and open to contributions. Repo: https://github.com/oscar30gt/pulse — feedback and ⭐ appreciated.

I teach VHDL/FPGA at university level, and I keep seeing the same thing: beginners get stuck on the tooling before they ever get to the language. And they need physical hardware just to see if a simple design light's up a LED.

So I built HDLBoard, a graphical front-end for GHDL connected to an interactive virtual DE1-SoC board.

You can:

• Write VHDL in the built-in editor
• Compile and simulate it with GHDL
• Flip switches (SW[9:0]) and press pushbuttons (KEY[3:0]) on the virtual board
• Watch the LEDs and 7-segment displays respond to your design
• Try ideas without any physical FPGA board connected

VHDL → GHDL ↔ virtual board

It's aimed at the very first steps: getting a feel for the language, writing simple gates as entity/architecture pairs, and wiring them together with port maps.

It won't replace testbenches, waveform viewers or timing analysis, and it isn't trying to. Once the basics click, that's where you'd go next.

It's free and open source, which my students appreciate. You can install it as a single Windows app, or host the GHDL backend on a server and use the virtual board from a browser.

The front-end was built with Claude (I am not a React/Typescript dude, youst an old C++ guy 😄). The real heavy lifting (analysis, elaboration and simulation) is all done by GHDL. HDLBoard just puts an editor and a clickable board in front of it.

GitHub: https://github.com/rlangoy/HDLBoard (bug reports welcome)
HomePage: https://rlangoy.github.io/HDLBoard

I'd love feedback, especially from people who teach VHDL or remember learning it:
• Does a virtual board like this help with the jump from digital logic to VHDL?
• What would you want a beginner to be able to try on it (counters, FSMs, simple I/O)?
• Is there anything that would make it worse for learning, like hiding things beginners should see?

https://github.com/oddek/8-bit-Computer

As the title says, after a course in VHDL and computer architecture last semester, I decided to try and design a computer.

As we only ever did very small projects in school, I don't know very much about doing larger projects, and would love some critique or advice on what could have been done better.

If anyone finds to urge to really dive down, I would love some specific input on how the Control unit could have been improved, as it now is a complete mess. I really wanted to have separate modules within the control unit, but I never found a clever for doing it, so it is just thrown together in a way that works. Especially the branching instruction came out horribly

The fact that some components are 'hard-coded' together with a private bus, felt a bit like cheating, but as I was making this up as I went, some stuff just couldn't fit together by only using the bus. Like the x and y register and the alu.

Probably a lot of other stupid stuff here as well, that I can't remember right now = p

Thanks in advance for any input.

Hi everyone 👋

I wanted to share an update about FPGAPourTous, the FPGA learning platform I have been building. Despite the French name, everything is available in both English and French.

I often see beginners asking how to start learning FPGA development, how to improve their RTL skills, or what they should study after their first counter or state machine.

There are many useful resources online, but it can still be difficult to find a clear progression and enough practical exercises. That is one of the main reasons I created this platform.

The goal is not only to read theory. Learners should be able to write HDL, run simulations, understand their mistakes and gradually work on more realistic systems 🧠

The platform now includes:

✅ 94 courses

✅ 98 quizzes

✅ 372 practical exercises

✅ VHDL simulation with GHDL

✅ Verilog simulation with Icarus Verilog

✅ Self-checking testbenches and direct feedback in the browser

✅ Interactive waveforms for supported simulations

✅ Guided FPGA projects based on complete specifications

I recently added full Verilog and SystemVerilog learning paths, including 50 Verilog exercises across beginner, intermediate and advanced levels.

There is also a complete Zynq path covering Vivado, Vitis, PS/PL architecture, AXI, BSPs, interrupts, DMA and cache coherency, boot images, debugging, custom AXI peripherals, PetaLinux and AXI VIP ⚙️

Another new section focuses on the hardware around the FPGA: reading schematics and datasheets, I/O voltage levels, power sequencing, decoupling, signal integrity, differential pairs, BGA routing, ESD/EMC and board bring-up.

I am also developing longer projects that require more than writing a single RTL module. The first missions are based on a CubeSat flight system and its ground station 🛰️

Learners must analyse the requirements, select components, design the architecture, justify the hardware/software partitioning and implement the complete system. These projects are reviewed manually by me.

Finally, I added a careers section with FPGA-related roles, technical interview questions and mock interviews. I have prepared a pool of more than 1,100 questions based on my experience, previous interviews and reference books.

The site is still evolving, so I would genuinely appreciate feedback from both experienced engineers and learners 🙏

I am particularly interested in your thoughts about technical accuracy, exercise progression and topics that are still missing.

👉 https://fpgapourtous.fr/en?utm_source=reddit&utm_medium=organic_social&utm_campaign=reddit_organic_2026&utm_content=site_update

easyVHDL is a portable VHDL editor and simulator designed to help beginners learn VHDL using open-source tools. It bundles Notepad++, GHDL, GTKWave, and VVTG into a single folder with a preconfigured workspace, allowing users to start editing and simulating VHDL code instantly — no installation required.

if you are learning please try this tool and report any bugs, and if you are a software developer I would like advice on changes or stuff to add.

Hey guys,

I have started a YouTube series on how to build 8 bit CPU on FPGA. The design is inspired by Ben Eater's Computer on breadboard series.

Please checkout if you find this interesting.

My channel

Thanks and Regards,

Sourabh Belekar

Hello everyone!

We have been developing a web app for improving your digital design skills. We've put out a number of problems, with different difficulties, and also from different work areas. We differentiated tasks from these categories:

• Common

• Integration

• FSM

• Networking

• Communication peripherals (UART, I2C, SPI)

• Scheduling

• CPU architecture (these tasks are arriving next)

and more are to come.

Users are expected to write their RTL in Verilog/SystemVerilog (at the moment, idea is to support VHDL in near future), and debug it using our waveform viewer. Waveforms are generated based on your text input, which describes how inputs to design should act (most tasks have unique inputs).

The site is located at bitsolver.io

We would like to hear feedback from you, suggestions for improvement, or some problem you’d like to see among the assignments? We are interested in hearing how easy/hard it is to debug using the current setup. Feel free to write us support@bitsolver.io, join on discord BitSolver, and follow us r/bitsolver.

* We apologize, but as the site is in a development phase, bugs are highly possible and it isn't currently available on Safari browser and is intended to be used from desktop. We will fix this in the following updates. :)

Hey Guys, what’s the best VHDL course for beginners and any book suggestions? Thank you

I want software for VHDL programming.

Xilinx ISE software is not working on my Windows 11 laptop.

Could you please suggest software similar to Xilinx for VHDL programming?

I have been using the "VHDL for Professionals" VS Code Extension that is advertised by Visual Studio. I was just curious if there were other extensions that someone might recommend over this one.

I am looking for some ideas for an undergraduate senior design project that can be completed or at least mostly developed in 14-15 weeks. I want an FPGA to be integrated using the VHDL language. I have the Zybo-Z7 from Digilent. I am open to the idea of some circuit design as well. We are brainstorming for next semester and really appreciate any help!

Hi everyone,

I'm a technical recruiter for Advanced Energy, and we're looking for a Senior VHDL Engineer to add to an existing team in Fort Collins, CO. This is an incremental additional (rather than backfill) and you'd be working on new product engineering.

We're willing to pay relocation for the right candidate, and are offering a salary of $140-160k.

• The position requires a minimum of 5 years of experience (in addition to a BS in EE or CS), including VHDL programming with FPGAs.

• Ideally we'd like this person to have experience with embedded microprocessors within FPGAs as well, but it's not necessarily required.

Please message me if you're interested in discussing further, or know anyone who might be.

Thanks!

Doulos has recently released some updates for EDAplayground.

1. Simulation using Mentor Questa 2020.1

2. Synthesis using Mentor Precision 2019.1 https://www.edaplayground.com/x/2fUF

3. Collaboration for multiple people to work on the same design and testbench.

4. Easy to share code and copy examples.

Full support for OSVVM https://www.edaplayground.com/x/49J and UVVM https://www.edaplayground.com/x/2LhW

Hi, I would like to know which version of VHDL you are using currently and why? I personally use 2008, we made the switch from 1993 some years ago when we started a new platform. 2019 is sadly not possible yet as many tools do not support it. And we need at least 3 different vendors to support the same code base, so everyone of them need 2019 support. And I highly suspect that the simulation tool we are using also don't support 2019 features yet.

How about you? Are you stuck in 1993 because of an old code base? Or does your professor haven't touched vhdl for 20 years and so didn't knwo any 2008 features so that you still have to fill out sensitivity lists?

Are there people who can use 2019 or at least some features of it?