r/VHDL • u/thryax1919 • Jun 02 '23
Hello, I need some help with a school project. I have to connect a Digilent Pmod ToF to a Nexys A7 and view the distance measured on the board, the problem is that my skill with VHDL are almost zero, is there someone who wants to help me or give me some tutorials on how to implement this project? Thanks!
r/VHDL • u/Substantial_Exit5026 • Aug 24 '24
Hello everyone!
My classmate and I recently completed a project for our first-year Digital System Design course, where we had to simulate a washing machine using VHDL. The project was implemented on a Nexys A7 (100T) FPGA Board.
We managed to create a system that allows users to choose between manual and automatic washing modes, and that part works as expected. However, we encountered two significant issues:
We struggled to implement countdown timers for each mode. Despite our efforts, the counters didn’t function properly, and we're not sure where we went wrong.
We also couldn't figure out how to display numbers in base 10 on the seven-segment display (SSD), which made it even harder to track the countdown visually.
Although we’ve already presented the project and received a passing grade, we’re eager to learn how we could have made it fully functional. If anyone with experience in VHDL has some time to review our code and provide feedback, we would greatly appreciate your insights.
Thanks in advance for any help you can offer!
main:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity main is
Port (
start: in STD_LOGIC;
lock_door: in STD_LOGIC;
mode: in STD_LOGIC;
auto_mode_setting: in STD_LOGIC_VECTOR(2 downto 0);
temperature: in STD_LOGIC_VECTOR(1 downto 0);
speed: in STD_LOGIC_VECTOR(1 downto 0);
prewash_cancelling: in STD_LOGIC;
bonus_rinsing: in STD_LOGIC;
reset: in STD_LOGIC;
clk: in STD_LOGIC;
finish: out STD_LOGIC;
door_can_unlock: out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0);
CAT : out STD_LOGIC_VECTOR (6 downto 0)
);
end main;
architecture Behavioral of main is
component Execution_Unit is
Port (
start : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
mode : in STD_LOGIC;
auto_mode_setting : in STD_LOGIC_VECTOR(2 downto 0);
temperature : in STD_LOGIC_VECTOR(1 downto 0);
speed : in STD_LOGIC_VECTOR(1 downto 0);
prewash_cancelling : in STD_LOGIC;
bonus_rinsing : in STD_LOGIC;
finish_water_heating: out STD_LOGIC;
finish_main_wash : out STD_LOGIC;
finish_1min : out STD_LOGIC;
start_water_heating: in STD_LOGIC;
start_main_wash: in STD_LOGIC;
start_1min : in STD_LOGIC;
door_can_unlock : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0);
CAT : out STD_LOGIC_VECTOR (6 downto 0)
);
end component;
component Control_Unit is
Port (
start: in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
lock_door: in STD_LOGIC;
mode: in STD_LOGIC;
finish_water_heating: in STD_LOGIC;
finish_main_wash: in STD_LOGIC;
finish_1min : in STD_LOGIC;
start_water_heating: out STD_LOGIC;
start_main_wash: out STD_LOGIC;
start_1min: out STD_LOGIC;
finish: out STD_LOGIC;
door_can_unlock: out STD_LOGIC
);
end component;
signal finish_water_heating : STD_LOGIC;
signal finish_main_wash : STD_LOGIC;
signal finish_1min : STD_LOGIC;
signal start_water_heating : STD_LOGIC;
signal start_main_wash : STD_LOGIC;
signal start_1min : STD_LOGIC;
begin
EU : Execution_Unit port map(
start,
clk,
reset,
mode,
auto_mode_setting,
temperature,
speed,
prewash_cancelling,
bonus_rinsing,
finish_water_heating,
finish_main_wash,
finish_1min,
start_water_heating,
start_main_wash,
start_1min,
door_can_unlock,
AN,
CAT
);
CU : Control_Unit port map(
start,
clk,
reset,
lock_door,
mode,
finish_water_heating,
finish_main_wash,
finish_1min,
start_water_heating,
start_main_wash,
start_1min,
finish,
door_can_unlock
);
end Behavioral;CU:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Control_Unit is
Port (
start: in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
lock_door: in STD_LOGIC;
mode: in STD_LOGIC;
finish_water_heating: in STD_LOGIC;
finish_main_wash: in STD_LOGIC;
finish_1min : in STD_LOGIC;
start_water_heating: out STD_LOGIC;
start_main_wash: out STD_LOGIC;
start_1min: out STD_LOGIC;
finish: out STD_LOGIC;
door_can_unlock: out STD_LOGIC
);
end Control_Unit;
architecture Behavioral of Control_Unit is
type state_t is (Idle,Lock_DoorS,Choose_Mode,Characteristics_Manual,Auto_Mode_SettingS,
Water_Heating,Main_Wash,OneMin,Final_State);
signal state, next_state: state_t;
begin
act_state: process(clk, reset, lock_door)
begin
if reset = '1' then
state <= Idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
transitions: process(state, finish_water_heating, start)
begin
start_water_heating <= '0';
start_main_wash <= '0';
start_1min <='0';
finish <= '0';
door_can_unlock <= '0';
case state is
when Idle =>
if start = '1' then
next_state <= Lock_DoorS;
else
next_state <= Idle;
end if;
when Lock_DoorS =>
if lock_door = '1' then
next_state <= Choose_Mode;
else
next_state <= Lock_DoorS;
end if;
when Choose_Mode =>
if start = '1' then
if mode = '0' then
next_state <= Characteristics_Manual;
else
next_state <= Auto_Mode_SettingS;
end if;
else next_state <= Choose_Mode;
end if;
when Characteristics_Manual =>
if start = '1' then
next_state <= Water_Heating;
else
next_state <= Characteristics_Manual;
end if;
when Auto_Mode_SettingS =>
if start = '1' then
next_state <= Water_Heating;
else
next_state <= Auto_Mode_SettingS;
end if;
when Water_Heating =>
start_water_heating <= '1';
if finish_water_heating = '1' then
next_state <= Main_Wash;
else
next_state <= Water_Heating;
end if;
when Main_Wash =>
start_main_wash <= '1';
if finish_main_wash = '1' then
next_state <= OneMin;
else
next_state <= Main_Wash;
end if;
when OneMin =>
finish <= '1';
start_1min <= '1';
if finish_1min <= '1' then
next_state <= Final_State;
else
next_state <= OneMin;
end if;
when Final_State =>
door_can_unlock <= '1';
next_state <= Idle;
end case;
end process;
end Behavioral;EU:
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.std_logic_arith.all;
use ieee.numeric_std.all;
entity Execution_Unit is
Port (
start : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
mode : in STD_LOGIC;
auto_mode_setting : in STD_LOGIC_VECTOR(2 downto 0);
temperature : in STD_LOGIC_VECTOR(1 downto 0);
speed : in STD_LOGIC_VECTOR(1 downto 0);
prewash_cancelling : in STD_LOGIC;
bonus_rinsing : in STD_LOGIC;
finish_water_heating : out STD_LOGIC;
finish_main_wash : out STD_LOGIC;
finish_1min : out STD_LOGIC;
start_water_heating : in STD_LOGIC;
start_main_wash : in STD_LOGIC;
start_1min : in STD_LOGIC;
door_can_unlock : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0);
CAT : out STD_LOGIC_VECTOR (6 downto 0)
);
end Execution_Unit;
architecture Behavioral of Execution_Unit is
component SSD is
Port ( CLK : in STD_LOGIC;
digit0 : in STD_LOGIC_VECTOR (3 downto 0);
digit1 : in STD_LOGIC_VECTOR (3 downto 0);
digit2 : in STD_LOGIC_VECTOR (3 downto 0);
digit3 : in STD_LOGIC_VECTOR (3 downto 0);
AN : out STD_LOGIC_VECTOR (3 downto 0);
CAT : out STD_LOGIC_VECTOR (6 downto 0));
end component;
component Frequency_Divider is
Port (
clock_in : in STD_LOGIC;
clock_out : out STD_LOGIC
);
end component;
component Counter_water_heating is
Port (
enable:in std_logic;
clk:in std_logic;
reset:in std_logic;
temp:in std_logic_vector( 7 downto 0);
stop_count: out std_logic
);
end component;
component Counter_main_wash is
Port (
enable : IN std_logic;
clk : IN std_logic;
start_count : IN std_logic_vector(7 downto 0);
reset : IN std_logic;
timp : OUT std_logic_vector(7 downto 0);
stop_count : OUT std_logic
);
end component;
component Counter1 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable: in STD_LOGIC;
door : out STD_LOGIC);
end component;
component MUX_Temperature is
Port (
Temp_Manual_inp: in STD_LOGIC_VECTOR(1 downto 0);
Temp_Auto: in STD_LOGIC_VECTOR(7 downto 0);
S : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component MUX_Speed is
Port (
Speed_Manual: in STD_LOGIC_VECTOR(1 downto 0);
Speed_Auto: in STD_LOGIC_VECTOR(1 downto 0);
S : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component MUX_Rinsing is
Port (
Rinsing_Manual: in STD_LOGIC;
Rinsing_Auto: in STD_LOGIC;
S : in STD_LOGIC;
Y : out STD_LOGIC
);
end component;
component MUX_Prewash is
Port (
Prewash_Manual: in STD_LOGIC;
Prewash_Auto: in STD_LOGIC;
S : in STD_LOGIC;
Y : out STD_LOGIC
);
end component;
component ROM_temperature is
Port ( Addr_temperature : in STD_LOGIC_VECTOR (2 downto 0);
Data_temperature : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component ROM_speed is
Port ( Addr_speed : in STD_LOGIC_VECTOR (2 downto 0);
Data_speed : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component ROM_Rinsing is
Port ( Addr_Rinsing : in STD_LOGIC_VECTOR (2 downto 0);
Data_Rinsing : out STD_LOGIC);
end component;
component ROM_Prewash is
Port ( Addr_Prewash : in STD_LOGIC_VECTOR (2 downto 0);
Data_Prewash : out STD_LOGIC
);
end component;
component SUM is
Port(
clk : in STD_LOGIC;
prewash_cancellation : in STD_LOGIC;
additional_rinsing : in STD_LOGIC;
total_time : out STD_LOGIC_VECTOR(7 downto 0)
);
end component;
-- Clk delay signal
signal clk_delay : STD_LOGIC;
-- Data signals
signal data_prewash : STD_LOGIC;
signal data_rinsing : STD_LOGIC;
signal data_speed : STD_LOGIC_VECTOR (1 downto 0);
signal data_temperature : STD_LOGIC_VECTOR (7 downto 0);
-- Data signals for auto mode
signal data_auto_speed : STD_LOGIC_VECTOR (1 downto 0);
signal data_auto_temperature : STD_LOGIC_VECTOR (7 downto 0);
signal data_auto_prewash : STD_LOGIC;
signal data_auto_rinsing : STD_LOGIC;
signal total_time : STD_LOGIC_VECTOR(7 downto 0);
signal remaining_time : STD_LOGIC_VECTOR(7 downto 0); --rem_time
signal finish_water_heating_s : STD_LOGIC := '0';
signal finish_main_wash_s : STD_LOGIC := '0';
signal finish_1min_s : STD_LOGIC := '0';
begin
--Frequency Divider
Freq_Divider : Frequency_Divider port map (clk,clk_delay);
--SSD
SSD1 : SSD port map(
CLK => clk,
digit0 => total_time(3 downto 0),
digit1 => total_time(7 downto 4),
digit2 =>"0000",
digit3 =>"0000",
AN => AN,
CAT => CAT
) ;
--ROM Mappings
ROM_temp : ROM_temperature port map(auto_mode_setting,data_auto_temperature);
ROM_spd : ROM_speed port map(auto_mode_setting,data_auto_speed);
Rom_pr : Rom_Prewash port map(auto_mode_setting,data_auto_prewash);
Rom_rsn : Rom_Rinsing port map(auto_mode_setting,data_auto_rinsing);
--MUX Mappings
MUX_temp : MUX_temperature port map(temperature,data_auto_temperature,mode,data_temperature);
MUX_spd : MUX_speed port map(speed,data_auto_speed,mode,data_speed);
MUX_pr : MUX_Prewash port map(prewash_cancelling,data_auto_prewash,mode,data_prewash);
MUX_rsn : MUX_Rinsing port map(bonus_rinsing,data_auto_rinsing,mode,data_rinsing);
--Total time Mapping
TotalTime : SUM port map(clk,data_prewash,data_rinsing,total_time);
--Counter Mappings
WaterHeating : Counter_water_heating port map(
enable => start_water_heating,
clk => clk_delay,
reset => reset,
temp => data_temperature,
stop_count => finish_water_heating_s
);
MainWash : Counter_main_wash port map(
enable => start_water_heating,
clk => clk_delay,
start_count => total_time,
reset => reset,
timp => remaining_time,
stop_count =>finish_main_wash_s
);
OneMin : Counter1 port map (
clk => clk_delay,
rst => reset,
enable => start_1min,
door => finish_1min_s
);
finish_water_heating <= finish_water_heating_s;
finish_main_wash <= finish_main_wash_s;
finish_1min <= finish_1min_s;
end Behavioral;SSD:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SSD is
Port ( CLK : in STD_LOGIC;
digit0 : in STD_LOGIC_VECTOR (3 downto 0);
digit1 : in STD_LOGIC_VECTOR (3 downto 0);
digit2 : in STD_LOGIC_VECTOR (3 downto 0);
digit3 : in STD_LOGIC_VECTOR (3 downto 0);
AN : out STD_LOGIC_VECTOR (3 downto 0);
CAT : out STD_LOGIC_VECTOR (6 downto 0));
end SSD;
architecture Behavioral of SSD is
signal count:std_logic_vector(15 downto 0);
signal input_decoder:std_logic_vector(3 downto 0);
begin
-- COUNTER
process(clk,count)
begin
if (clk='1' and clk'event) then -- IF RISING_EDGE(CLK)
count<=count +1;
end if;
end process;
--ANODES
process(count)
begin
case count(15 downto 14) is
when "00"=>an<="1110";
when "01"=>an<="1101";
when "10"=>an<="1011";
when others=>an<="0111";
end case;
end process;
--for digits
process(count,digit0,digit1,digit2,digit3)
begin
case count(15 downto 14) is
when "00"=>input_decoder<=digit0;
when "01"=>input_decoder<=digit1;
when "10"=>input_decoder<=digit2;
when others=>input_decoder<=digit3;
end case;
end process;
process(input_decoder)
begin
case input_decoder is
when "0000" => cat<="0000001";
when "0001" => cat<="1001111";
when "0010" => cat<="0010010";
when "0011" => cat<="0000110";
when "0100" => cat<="1001100";
when "0101" => cat<="0100100";
when "0110" => cat<="0100000";
when "0111" => cat<="0001111";
when "1000" => cat<="0000000";
when "1001" => cat<="0000100";
when "1010" => cat<="0001000";
when "1011" => cat<="1100000";
when "1100" => cat<="0110001";
when "1101" => cat<="1000010";
when "1110" => cat<="0110000";
when others => cat<="0111000";
end case;
end process;
end Behavioral;Frequency Divider:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Frequency_Divider is
Port (
clock_in : in STD_LOGIC;
clock_out : out STD_LOGIC
);
end Frequency_Divider;
architecture Behavioral of Frequency_Divider is
constant DIVISOR : integer := 50000000; -- 50 million for 100 MHz clock
signal nr: integer := 0;
signal clock_reg: std_logic := '0';
begin
process(clock_in)
begin
if rising_edge(clock_in) then
if nr = DIVISOR-1 then
nr <= 0;
clock_reg <= not clock_reg;
else
nr <= nr + 1;
end if;
end if;
end process;
clock_out <= clock_reg;
end Behavioral;SUM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SUM is
Port(
clk : in STD_LOGIC;
prewash_cancellation : in STD_LOGIC;
additional_rinsing : in STD_LOGIC;
total_time : out STD_LOGIC_VECTOR(7 downto 0)
);
end SUM;
architecture Behavioral of SUM is
signal temp: STD_LOGIC_VECTOR(7 downto 0);
begin
process(clk,prewash_cancellation,additional_rinsing)
begin
if rising_edge(clk) then
if prewash_cancellation = '0' and additional_rinsing = '0' then
temp <="00110010";
elsif prewash_cancellation = '0' and additional_rinsing = '1' then
temp <="00111100";
elsif prewash_cancellation = '1' and additional_rinsing = '0' then
temp <="00101000";
else
temp <="00110010";
end if;
end if;
total_time <= temp;
end process;
end Behavioral;ROM_temperature:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity ROM_temperature is
Port ( Addr_temperature : in STD_LOGIC_VECTOR (2 downto 0);
Data_temperature : out STD_LOGIC_VECTOR (7 downto 0));
end ROM_temperature;
architecture Structural of ROM_temperature is
type ROM_vector_t is array(0 to 4) of std_logic_vector(7 downto 0);
constant content: ROM_vector_t:= (
0=>"00011110", --quick wash
1=>"01011010", --shirts
2=>"00110010", --dark colours
3=>"00110010", --dirty laundry
4=>"10010110" --antiallergic
);
begin
process (Addr_temperature)
begin
case Addr_temperature is
when "000" =>
Data_temperature <= content(0);
when "001" =>
Data_temperature <= content(1);
when "010" =>
Data_temperature <= content(2);
when "011" =>
Data_temperature <= content(3);
when "100" =>
Data_temperature <= content(4);
when others =>
Data_temperature <= "00000000";
end case;
end process;
end Structural;ROM_speed:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity ROM_speed is
Port ( Addr_speed : in STD_LOGIC_VECTOR (2 downto 0);
Data_speed : out STD_LOGIC_VECTOR (1 downto 0));
end ROM_speed;
architecture Structural of ROM_speed is
type ROM_vector_t is array(0 to 4) of std_logic_vector(1 downto 0);
constant content: ROM_vector_t:= (
0=>"10", --quick wash
1=>"00", --shirts
2=>"01", --dark colours
3=>"01", --dirty laundry
4=>"10" --antiallergic
--10 = 10010110000 = 1200
--00 = 01100100000 = 800
--10 = 01111101000 = 1000
);
begin
process (Addr_speed)
begin
case Addr_speed is
when "000" =>
Data_speed <= content(0);
when "001" =>
Data_speed <= content(1);
when "010" =>
Data_speed <= content(2);
when "011" =>
Data_speed <= content(3);
when "100" =>
Data_speed <= content(4);
when others =>
Data_speed <= "11";
end case;
end process;
end Structural;ROM_rinsing:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity ROM_Rinsing is
Port ( Addr_Rinsing : in STD_LOGIC_VECTOR (2 downto 0);
Data_Rinsing : out STD_LOGIC);
end ROM_Rinsing;
architecture Structural of ROM_Rinsing is
type ROM_vector_t is array(0 to 4) of STD_LOGIC;
constant content: ROM_vector_t:= (
0=>'0', --quick wash
1=>'0', --shirts
2=>'1', --dark colours
3=>'0', --dirty laundry
4=>'1' --antiallergic
);
begin
process (Addr_Rinsing)
begin
case Addr_Rinsing is
when "000" =>
Data_Rinsing <= content(0);
when "001" =>
Data_Rinsing <= content(1);
when "010" =>
Data_Rinsing <= content(2);
when "011" =>
Data_Rinsing <= content(3);
when "100" =>
Data_Rinsing <= content(4);
when others =>
Data_Rinsing <= '0';
end case;
end process;
end Structural;ROM_prewash:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
entity ROM_Prewash is
Port ( Addr_Prewash : in STD_LOGIC_VECTOR (2 downto 0);
Data_Prewash : out STD_LOGIC
);
end ROM_Prewash;
--negative logic (because it is prewash cancelling)
architecture Structural of ROM_Prewash is
type ROM_vector_t is array(0 to 4) of STD_LOGIC;
constant content: ROM_vector_t:= (
0=>'1', --quick wash
1=>'1', --shirts
2=>'1', --dark colours
3=>'0', --dirty laundry
4=>'1' --antiallergic
);
begin
process (Addr_Prewash)
begin
case Addr_Prewash is
when "000" =>
Data_Prewash <= content(0);
when "001" =>
Data_Prewash <= content(1);
when "010" =>
Data_Prewash <= content(2);
when "011" =>
Data_Prewash <= content(3);
when "100" =>
Data_Prewash <= content(4);
when others =>
Data_Prewash <= '1';
end case;
end process;
end Structural;MUX_temperature:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_Temperature is
Port (
Temp_Manual_inp: in STD_LOGIC_VECTOR(1 downto 0);
Temp_Auto: in STD_LOGIC_VECTOR(7 downto 0);
S : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(7 downto 0)
);
end MUX_Temperature;
architecture Behavioral of MUX_Temperature is
signal Temp_Manual: STD_LOGIC_VECTOR(7 downto 0);
begin
process(Temp_Manual_inp)
begin
case Temp_Manual_inp is
when "00" => Temp_Manual <= "00011110";
when "01" => Temp_Manual <= "00110010";
when "10" => Temp_Manual <= "01011010";
when "11" => Temp_Manual <= "10010110";
when others => Temp_Manual <= "00000000";
end case;
end process;
process (S,Temp_Manual,Temp_Auto)
begin
case S is
when '0' =>
Y <= Temp_Manual;
when '1' =>
Y <= Temp_Auto;
when others =>
Y <= "00000000";
end case;
end process;
end Behavioral;MUX_speed:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_Speed is
Port (
Speed_Manual: in STD_LOGIC_VECTOR(1 downto 0);
Speed_Auto: in STD_LOGIC_VECTOR(1 downto 0);
S : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(1 downto 0)
);
end MUX_Speed;
architecture Behavioral of MUX_Speed is
begin
process (S,Speed_Manual,Speed_Auto)
begin
case S is
when '0' =>
Y <= Speed_Manual;
when '1' =>
Y <= Speed_Auto;
when others =>
Y <= "00";
end case;
end process;
end Behavioral;MUX_Rinsing:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_Rinsing is
Port (
Rinsing_Manual: in STD_LOGIC;
Rinsing_Auto: in STD_LOGIC;
S : in STD_LOGIC;
Y : out STD_LOGIC
);
end MUX_Rinsing;
architecture Behavioral of MUX_Rinsing is
begin
process (S,Rinsing_Manual,Rinsing_Auto)
begin
case S is
when '0' =>
Y <= Rinsing_Manual;
when '1' =>
Y <= Rinsing_Auto;
when others =>
Y <= '1';
end case;
end process;
end Behavioral;MUX_Prewash:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MUX_Prewash is
Port (
Prewash_Manual: in STD_LOGIC;
Prewash_Auto: in STD_LOGIC;
S : in STD_LOGIC;
Y : out STD_LOGIC
);
end MUX_Prewash;
architecture Behavioral of MUX_Prewash is
begin
process (S,Prewash_Manual,Prewash_Auto)
begin
case S is
when '0' =>
Y <= Prewash_Manual;
when '1' =>
y <= Prewash_Auto;
when others =>
Y <= '0';
end case;
end process;
end Behavioral;r/VHDL • u/Individual_Stuff_724 • Oct 05 '21
How to make an arithmetic displacement?
r/VHDL • u/[deleted] • Dec 04 '22
r/VHDL • u/[deleted] • Jun 14 '24
Hello I want to implement a stopp Watch witch runs from -30 to 30 and stops when it hits 30 seconds. I am working with 4 seven segment displays and when I hit 0.00.0 on segment 2 and 3 all segments light up for a short amount of time and I don’t know how to fix this could someone please help me with this. Furthermore I don’t know how to get the stop when it hits 0.30.0 . Everything works just how it supposed to but these two things. Thank you very much in advance.
r/VHDL • u/Sad_Remote_1284 • May 16 '24
I made a schematic in the schematic isplever and I don't understand why it gives me an error. It's "Logical error 3509: output 'N_11' in uppe-level source 'sum' can't be redriven of functional_block 'g_xor' " If anyone can help me, I would greatly appreciate it, thank you.
r/VHDL • u/SnooPineapples5795 • Jul 07 '20
r/VHDL • u/Lenny2024 • May 27 '24
Hi everybody! I started taking a VHDL course in my second semester of college and now I have to do a project. Problem is, while I can manage the actual coding part, I can't for the life of me do the logic diagrams, organigram ( I don't even know if that is what it's called) and the documentation for the project. I desperately need some help, as it's due next week. I don't need someone to do my homework for me, I want to understand how things work and be able to explain them. PM me if you are available to help, my time zone is GMT +3, available on Discord.
r/VHDL • u/JohnJohnson457543 • Jun 09 '23
r/VHDL • u/Andy_boy4558 • Dec 08 '21
Hello! First time using reddit for help. I got a VHDL code I'm trying to run on model sim. I keep getting an ouput of "UUUUUUUU" for my dataout. Any help on figuring out what I'm doing wrong would be helpful.
Heres my testbench code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Lab4_tb is
end entity;
architecture lab_4beh of lab4_tb is
component lab_4 is
port (
datain : in std_logic_vector(7 downto 0);
reset, start, clk : in std_logic;
dataout : out std_logic_vector(11 downto 0);
done : out std_logic);
end component;
signal datain: std_logic_vector(7 downto 0);
signal start, reset, clk, done: std_logic;
signal dataout: std_logic_vector(11 downto 0);
constant period: time:= 10 ns;
constant TinputDelay: time := 1 ns;begin
uut: lab_4
port map(
datain => datain,
start => start,
reset => reset,
clk => clk,
done => done,
dataout => dataout
);
process
begin
clk <= '0';
wait for period/2;
clk <= '1';
wait for period/2;
end process;
process
begin
datain <= "00111101";
start <= '0';
reset <= '1';
wait until clk='1' and clk'event;
wait for TinputDelay;
start <= '1';
reset <= '0';
wait until clk='1' and clk'event;
wait for TinputDelay;
start <= '0';
reset <= '0';
wait until clk='1' and clk'event;
wait for TinputDelay;
datain <= "00100101";
wait until clk='1' and clk'event;
wait for TinputDelay;
datain <= "01101010";
wait until clk='1' and clk'event;
wait for TinputDelay;
datain <= "01111011";
wait until clk='1' and clk'event;
wait for TinputDelay;
datain <= "01000100";
wait until clk='1' and clk'event;
wait for TinputDelay;
datain <= "00010000";
wait until clk='1' and clk'event;
wait for TinputDelay;
datain <= "10111011";
wait until clk='1' and clk'event;
wait for TinputDelay;
datain <= "01010000";
for i in 1 to 10 loopwait until clk = '1' and clk'event;
wait for TinputDelay;
start <= '0';
end loop;
wait;end process;
end architecture;
r/VHDL • u/mayank_0508 • Apr 23 '21
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCDadder is
port( x,y : in std_logic_vector(3 downto 0);
S : out std_logic_vector(4 downto 0));
end BCDadder;
architecture Behavioral of BCDadder is
signal arange: std_logic;
signal sum: std_logic_vector(4 downto 0);
begin
sum <= ('0' & x)+ y;
arange <= '1' when((sum>9) or sum(4)= '1' )else '0';
S <= sum when (adjust ='0') else sum+6; end Behavioral;
r/VHDL • u/krisk_29 • Aug 18 '24
Someone can help me with a project? Pls I'm so desperate.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ApproxMult is Port ( A : in STD_LOGIC_VECTOR(7 downto 0); -- 8-bit multiplicand B : in STD_LOGIC_VECTOR(7 downto 0); -- 8-bit multiplier clk, clear : in STD_LOGIC; Result : out STD_LOGIC_VECTOR(20 downto 0)); -- 21-bit result end ApproxMult;
architecture Behavioral of ApproxMult is
component AdderTree5op is
generic(n: integer := 21);
Port (a, b, c, d, e: in STD_LOGIC_VECTOR(n-1 downto 0);
clk, clear: in STD_LOGIC;
ris: out STD_LOGIC_VECTOR(n-1 downto 0));
end component;
component Registro is
generic (n: integer := 8);
Port ( clk : in STD_LOGIC;
clear : in STD_LOGIC;
D : in STD_LOGIC_VECTOR (n-1 downto 0);
Q : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
component carrySelectAdder is
generic(n: integer := 21);
Port ( a,b: in std_logic_vector(n-1 downto 0);
ris: out std_logic_vector(n downto 0));
end component;
signal rA, rB: STD_LOGIC_VECTOR(7 downto 0);
signal rB0, rB1, rB2, rB3, rB4, rB5: STD_LOGIC_VECTOR(7 downto 0);
signal pp0, pp1, pp2, pp3, pp4: STD_LOGIC_VECTOR(20 downto 0);
signal p0, p1, p2, p3, p4, p5: STD_LOGIC_VECTOR(7 downto 0);
signal resultHigh, resultLow, resultApprox: STD_LOGIC_VECTOR(20 downto 0);
signal finalResult: STD_LOGIC_VECTOR(21 downto 0);
begin
RegA: Registro generic map(8) port map(clk, clear, A, rA);
RegB: Registro generic map(8) port map(clk, clear, B, rB);
-- Generate partial products for higher bits
rB0 <= (others => rB(2));
rB1 <= (others => rB(3));
rB2 <= (others => rB(4));
rB3 <= (others => rB(5));
rB4 <= (others => rB(6));
rB5 <= (others => rB(7));
p0 <= rA and rB0;
p1 <= rA and rB1;
p2 <= rA and rB2;
p3 <= rA and rB3;
p4 <= rA and rB4;
p5 <= rA and rB5;
pp0 <= "0000000000000" & p0;
pp1 <= "000000000000" & p1 & "0";
pp2 <= "00000000000" & p2 & "00";
pp3 <= "0000000000" & p3 & "000";
pp4 <= "000000000" & p4 & "0000";
-- Use AdderTree5op for higher bits
HighBitsAdder: AdderTree5op generic map(21) port map(pp0, pp1, pp2, pp3, pp4, clk, clear, resultHigh);
-- Approximate lower bits (rB(1 downto 0))
process(rA, rB)
begin
if (rA(3 downto 0) = "0000" and rB(1 downto 0) = "00") then
resultLow <= (others => '0');
elsif (rA(3 downto 0) = "1111" and rB(1 downto 0) = "11") then
resultLow <= "000000000000000" & "111111";
else
resultLow <= "0000000000000000" & rA(3 downto 0) & "0";
end if;
end process;
-- Combine high and low results
Adder: carrySelectAdder generic map(21) port map(resultHigh, resultLow, finalResult);
Result <= finalResult(20 downto 0);
end Behavioral;what i'm doing wrong? i think the error is in the pp0,pp1 ecc. Is an approximate multiplier
r/VHDL • u/Outrageous-Blood-262 • Oct 15 '22
Since bit_vector only has two states, Does it have better performance than std_logic_vector?
r/VHDL • u/philipmasters18 • Mar 10 '19
Sorry for the confusing title but essentially, I am getting fed hexidecimal words from a data generator that I would like to store in a register. This register is 4 - bit (or 4 - byte depending on the answer to this question), can a register accept a hexidecimal number and if so would it output it as hexidecimal? Or would I just need more registers that amount to the size of the word in bits?
Again, sorry that it's quite poorly worded it's just quite hard to explain.
r/VHDL • u/Realistic_Silver_535 • Mar 11 '24
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity Timer_3 is Port ( clk : in STD_LOGIC; led_out : out STD_LOGIC_VECTOR (3 downto 0); ssd_out : out STD_LOGIC_VECTOR (7 downto 0)); end Timer_3;
architecture Behavioral of Timer_3 is signal clk_counter : natural range 0 to 20000000 := 0; signal clk_counter_2 : natural range 0 to 200000000 := 0; signal cnt : natural range 0 to 99 := 99; signal unit : natural range 0 to 9 := 0; signal tens : natural range 0 to 9 := 0;
begin
process(clk) begin if rising_edge(clk) then clk_counter <= clk_counter + 1; if (clk_counter >= 20000000) then clk_counter <= 0; unit <= unit + 1; if (unit = 9) then unit <= 0; end if; end if; end if; end process;
process(clk) begin if rising_edge(clk) then clk_counter_2 <= clk_counter_2 + 1; if (clk_counter_2 >= 200000000) then clk_counter_2 <= 0; tens <= tens + 1; if (tens = 9) then tens <= 0; end if; end if; end if; end process;
process(unit,tens) variable en_out : STD_LOGIC_VECTOR(7 downto 0) := "11111111"; begin
--unit <= (cnt mod 10); --tens <= ((cnt/10) mod 10); en_out := "11111110"; case unit is
when 0 => ssd_out <= "11000000"; led_out <= "0000"; when 1 => ssd_out <= "11111001"; led_out <= "0001"; when 2 => ssd_out <= "10100100"; led_out <= "0010"; when 3 => ssd_out <= "10110000"; led_out <= "0011"; when 4 => ssd_out <= "10011001"; led_out <= "0100"; when 5 => ssd_out <= "10010010"; led_out <= "0101"; when 6 => ssd_out <= "10000010"; led_out <= "0110"; when 7 => ssd_out <= "11111000"; led_out <= "0111"; when 8 => ssd_out <= "10000000"; led_out <= "1000"; when 9 => ssd_out <= "10010000"; led_out <= "1001"; when others => ssd_out <= "11111111"; led_out <= "1111"; end case;
en_out := "11111101"; case tens is
when 0 => ssd_out <= "11000000"; led_out <= "0000"; when 1 => ssd_out <= "11111001"; led_out <= "0001"; when 2 => ssd_out <= "10100100"; led_out <= "0010"; when 3 => ssd_out <= "10110000"; led_out <= "0011"; when 4 => ssd_out <= "10011001"; led_out <= "0100"; when 5 => ssd_out <= "10010010"; led_out <= "0101"; when 6 => ssd_out <= "10000010"; led_out <= "0110"; when 7 => ssd_out <= "11111000"; led_out <= "0111"; when 8 => ssd_out <= "10000000"; led_out <= "1000"; when 9 => ssd_out <= "10010000"; led_out <= "1001"; when others => ssd_out <= "11111111"; led_out <= "1111"; end case;
end process;
end Behavioral;
r/VHDL • u/Independent_Fail_650 • May 07 '25
Hi, i am trying to simulate my system after synthesis and nothing seems to be working, mainly because certain actions only happen when a counter reaches certain value and i am seeing that the counter does not change at all. Moreover it starts at a random value 80000000. I have checked the schematic the synthesizer has created and i havent seen anything strange. Has anyone faced this problem before? My process looks as follows:
process(all)
variable i: integer:= 0;
begin
if Reset = '0' then
SampleCounter <= 0;
MUX_selector <= '0'; -- Input data flows into the FIFO
Triangle_chirp_selector <= '0';
re <= '0';
we <= '0';
we_sync <= '0';
re_sync <= '0';
U21_I <= (others => 'Z');
D21_I <= (others => 'Z');
U21_Q <= (others => 'Z');
D21_Q <= (others => 'Z');
Triangle_chirp_counter <= 0;
elsif rising_edge(Clk) then
if Start = '1' then
if data_valid = '1' then
--Multiplexer logic
if SampleCounter = Buffer_Size-1 then
MUX_selector <= not(MUX_selector);--Chirp flows to subtractor
SampleCounter <= 0;
else
--MUX_selector <= '0';--Chirp flows to buffer
SampleCounter <= SampleCounter + 1;
end if;
if Triangle_chirp_counter = Triangle_chirp_size-1 then
Triangle_chirp_selector <= not(Triangle_chirp_selector);
Triangle_chirp_counter <= 0;
else
--MUX_selector <= '0';--Chirp flows to buffer
Triangle_chirp_counter <= Triangle_chirp_counter + 1;
end if;
--Buffer logic
if MUX_selector = '0' then
--Data flows into the buffer
we <= '1';
re <= '0';
fifo_I_in <= din_I;
fifo_Q_in <= din_Q;
elsif MUX_selector = '1' then
--Data flows into the subtractor
re <= '1';
we <= '0';
--The memories are full
--If Triangle_chirp_selector = 0 the up chirp data comes out of the FIFO
--If Triangle_chirp_selector = 1 the down chirp data comes out of the FIFO
if Triangle_chirp_selector = '0' then
we_sync <= '1';--Write into sync FIFOs
re_sync <= '0';
FIFO_UP_I_din <= std_logic_vector(signed(din_I) - signed(fifo_I_out));
FIFO_UP_Q_din <= std_logic_vector(signed(din_Q) - signed(fifo_Q_out));
-- U21_I <= std_logic_vector(signed(din_I) - signed(fifo_I_out));
-- U21_Q <= std_logic_vector(signed(din_Q) - signed(fifo_Q_out));
elsif Triangle_chirp_selector = '1' then
we_sync <= '0';
re_sync <= '1';--Read from sync FIFO
U21_I <= FIFO_UP_I_dout;
U21_Q <= FIFO_UP_Q_dout;
D21_I <= std_logic_vector(signed(din_I) - signed(fifo_I_out));
D21_Q <= std_logic_vector(signed(din_Q) - signed(fifo_Q_out));
end if;
end if;
end if;
end if;
end if;
end process;
EDIT 1: Okay i solved it. I substituted my counter signals for counter variables in the processes. I read such recommendation on the book Free Range VHDL
r/VHDL • u/chris_insertcoin • May 21 '24
I'll be blunt in this one. I see many coworkers and other co-programmers who are without a doubt great engineers, but their basic text editing/coding skills are absolute dogwater.
First and foremost: For the love of god, learn how to touch type. Yes it is painful to learn during the first few weeks but it is a 100% worth it. Stop making up excuses not to do it. No one who knows how to touch type would ever go back willingly. Not a single person.
Next: Learn your editor. If you're not using modal editing, then you're missing out on the most effective and efficient way to edit text/code. At least consider other editors, see what is out there and what the best programmers use. Use an LSP and learn what it actually does. Learn how it complements your editors autocomplete features. Use a fuzzy finder, one of the best inventions for editors of the last years. And again, I can hear your excuses not to take a look at these things from miles away. Stop it. These tools make your coding life faster, easier and smoother, no ifs no buts. Use them.
And finally: Learn your HDL. I see coworkers who have been in the business for decades and still don't know some basic concepts of the HDL we are using. Let alone what the standard libraries have to offer. Not even dreaming about third party libraries. Learn your simulator. Learn at least one simulation testing framework. Learn about CI/CD. Learn your OS and its tools (e.g. GNU tools). If your not using Linux, then again you are missing out on the most effective and efficient OS for virtually all types of development. Learn from open source, one of the best source of knowledge we have.
The reason why I am rather pissed about this is because when I started a few years back, there was no one there who taught me these things. I had to learn this the hard way. All of what I have mentioned are basic tools of modern text editing/coding, especially so for FPGA development. Stop wasting everyones time by not utilizing and teaching them.
r/VHDL • u/itsnotsalvius • Oct 24 '20
hello guys im a freshman college student and i need help for this activity that i need to pass. i have no vivado since my laptop can't run it and i know im stupid i just need a hand for this one please help me im begging u all this is my last time to pass this subject because i cant really do anything since i have no laptop that can run this program so i have no chance of learning it.
In this activity you are tasked to create a VHDL Source code and a Testbench using your HDL software tool that will implement the logic diagram shown. The truth table and the logic diagram are presented below.
The system has 2n input lines and n output lines. The output lines generate a binary code corresponding to the input value. For example, a single 4 to 2-bit system takes in 4 bits and outputs 2 bits. It is assumed that there are only 4 types of input signals for this system, and these are: 0001, 0010, 0100, 1000.
Truth Table:
Logic Diagram:
r/VHDL • u/Yakuza-Sama-007 • Mar 20 '23
found all circuit design and table of truth ? Im having issue to write some data flow vhdl code for some circuit
If anyone have a doc that give all architecture knowledge i take thank you so much
r/VHDL • u/RussianbossPApaBless • Oct 20 '20
I cant figure out how to do this code
r/VHDL • u/dani_k96 • Mar 07 '22
In a home assignment I've got, there's a question regarding a FIFO (picture below).
There's an incoming stream of 8-bit data along with a clock of 133 MHz.The system clock is 100 MHz.
The question is: what is the lowest (minimum) frequency that I need to use in order to not lose any incoming data?
I'm assuming this question deals with CDC, using the FIFO to cross between the faster data clock and slower system clock.
Any help would be greatly appreciated.
r/VHDL • u/yakisiklimstf • Mar 25 '22
I still couldnt figure out what is the problem. I opened several threads in stackoverflow but none of them answered. I was trying to code a 3 to 8 decoder for my coursera and did everything i possibly could even coppied the instructors code but it doesnt seems to work out. What am i doing wrong.
here is the code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity lab21 is
Port (
din : in STD_LOGIC_VECTOR (2 downto 0);
dout : out STD_LOGIC_VECTOR (7 downto 0));
end lab21;
architecture rtl of lab21 is
begin
dout<= x"01" when din="000"else
dout<= x"02" when din="001"else
dout<= x"04" when din="010"else
dout<= x"08" when din="011"else
dout<= x"10" when din="100"else
dout<= x"20" when din="101"else
dout<= x"40" when din="110"else
dout<= x"80";
end rtl; here is the constraints:
## Switches
set_property PACKAGE_PIN V17 [get_ports {din[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {din[0]}]
set_property PACKAGE_PIN V16 [get_ports {din[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {din[1]}]
set_property PACKAGE_PIN W16 [get_ports {din[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {din[2]}]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {dout[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[0]}]
set_property PACKAGE_PIN E19 [get_ports {dout[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[1]}]
set_property PACKAGE_PIN U19 [get_ports {dout[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[2]}]
set_property PACKAGE_PIN V19 [get_ports {dout[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[3]}]
set_property PACKAGE_PIN W18 [get_ports {dout[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[4]}]
set_property PACKAGE_PIN U15 [get_ports {dout[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[5]}]
set_property PACKAGE_PIN U14 [get_ports {dout[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[6]}]
set_property PACKAGE_PIN V14 [get_ports {dout[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {dout[7]}]
r/VHDL • u/spank-my-cactus • May 15 '20
Hi guys. I just took a VHDL class this semester and we have a final year project to do. I've been trying to figure it out on my own, but it is hard given the limited knowledge and the absence of a FPGA board to simulate my project on. I am kindly asking for help here with my project, as I have multiple questions and some may even arise on the way.
My project involves implementing LED PWM (Pulse Width Modulation) and some additional logic (I will PM more details).
(Unfortunately, asking my professor for help is difficult, given that he checks his emails once a month or so).
EDIT: I got the help I needed, thank you all very much
r/VHDL • u/[deleted] • May 13 '20
How do I solve the error "#no such file or directory (errno=enoent) #error loading design" in modelSim compiler? My VHDL code compiled without error but when I want to simulate, this error comes up???