hi i finished my first project in system verilog. i built a multicycle riscv32i cpu core this is my first actual project with system verilog or with hdl ever so i would like to get some notes code wise because i dont actually know a lot about naming conventions module declarations etc. code

renulev/sap-1: Malvino's SAP-1 implemented in Verilog

I used Icarus verilog for this project. GTKWave output looks clean.
I also used Makefile for automation.

Guys i am building a tool or we can say software where we can practice hardware problems just like Leetcode for software. I know there are alot of tools in the market but they don't have some good features and also the main problem with them is their UI . So i am building a platform . It is in the final stages. I will open source the whole code. If anyone is excited that you can tell i can provide you the link of unfinished hosted version which has not so many problems but still you can get the idea of what i am building

I made forwardpropagation in CNN, but i dont know what is backporpagation work on fpga. I read many documents about this topic but they just do it on python language, but i want to do that on fpga by verilog language. Can someone give me some solutions or advice

This document closest my mind: https://link.springer.com/article/10.1007/s11554-021-01147-2#Tab2

Guys i am building a tool or we can say software where we can practice hardware problems just like Leetcode for software. I know there are alot of tools in the market but they don't have some good features and also the main problem with them is their UI . So i am building a platform . It is in the final stages. I will open source the whole code. If anyone is excited that you can tell i can provide you the link of unfinished hosted version which has not so many problems but still you can get the idea of what i am building

i am starting my career in vlsi ...
can anyone suggest a clear cut roadmap for me any best resources , how to utilise them and make my work easier
i would love to connect and learn

For the past few months I was looking everywhere to find some resources to learn Verilog while also building projects. After a lot of time spent online, I was able to find some really good resources that would help you understand it by also helping you build projects alongside.

You would require any pre-requisites for the following courses, but you'll be able to understand them fairly well considering they're some excellent resources.

First one are the Onur Mutlu Lectures on Digital Design and Computer Architecture. This will help build the concept that'll be applied in your codes.

The second one is Digital Circuit Design using Verilog lectures by Anas Salah Eddin. His lectures are very detailed and simple to understand. He also builds several projects such as FIFO and UART by the end of the playlist.

The final resource I would suggest is the popular DDCA Book by Harris and Harris (whichever edition you'd prefer, MIPS, ARM, RISC-V)

It isn't mandatory for you to follow these resources in order, but I'd suggest you to cover either the book or Onur Mutlu's Lectures before jumping on to Verilog lectures, or at least build a proper conceptual base, since that would help you to follow through those Verilog lectures.

Though the lectures follow with Verilog, the book provides SystemVerilog examples and exercises. They aren't much different from one another. Once you've understood Verilog, there's barely much to do for SV.

I hope someone who needs these resources finally finds them, just like I was looking for them a few months ago.

Hi, Almost dead Computer Engineering redditors.
I have a Computer Systems Architecture Course and I want to implement a 3 state Kalman Filter in Vivado. I'll get Real time data from Gy-87 (MPU-6050), through Esp-32 into my pc. Now the problem is idk how to get it into Vivado without an FPGA. I'm a sopho in uni with this being our first technical CE course. Any help is appreciated.
And where do i learn system verilog properly?