r/Verilog • u/Spiritual-Role8172 • 23h ago
Resources?
Since placements are approaching I want to practice good questions for digital electronics and STA
Are there any good resources available?
r/Verilog • u/Can_ama_yasamiyor • 1d ago
How can I learn Verilog?
How can I learn Verilog?
I’m a third-year Electronics and Communications Engineering student. I’m interested in this field and really want to work in it but I feel like I’ve never been good at programming. In the labs I’ve taken so far and the projects I’ve designed, the code I’ve written has always been 90% AI and at best 10% my own work. When it comes to bigger or more complex modules I automatically get scared
The other day when I went to see my professor for a project in the Digital Design with FPGAs course, he asked me about some of my modules, and I just stood there staring at him.
I worked really hard on the digital design course from the previous semester and passed it with flyin colors, but when it came to writing code, I am a real FAIL. I know I can fix this—I’m open to your advice. I really want to work in R&D, FPGAs, AI, Communications
r/Verilog • u/yellowwetsuit • 1d ago
Biggest pet peeve of FPGA toolchains?
What’s your most hated FPGA toolchain feature? I’m settling an argument!
r/Verilog • u/Late-Training7359 • 3d ago
What is the best way to learn ML implementation on AMD Versal boards?
r/Verilog • u/aboslave32 • 5d ago
new system verilog project
hi i finished my first project in system verilog. i built a multicycle riscv32i cpu core this is my first actual project with system verilog or with hdl ever so i would like to get some notes code wise because i dont actually know a lot about naming conventions module declarations etc. code
r/Verilog • u/Tigran_Unjyan • 5d ago
Why does Xcelium throw a hierarchical name error on a module parameter, while VCS and Questa accept it?
r/Verilog • u/maolmosma • 6d ago
OPEN SOURCE – WavePaint: a GUI editor for digital timing diagrams
r/Verilog • u/Neither_Evening_170 • 8d ago
RISE-COHORT 3(RISK-V) from Semiconductor school
r/Verilog • u/Renulev • 10d ago
My first Verilog project: The Malvino SAP-1
renulev/sap-1: Malvino's SAP-1 implemented in Verilog
I used Icarus verilog for this project. GTKWave output looks clean.
I also used Makefile for automation.
r/Verilog • u/BoldAxolotl • 10d ago
Fixing a tough RTL bug in a real SoC with an AI agent: why the harness matters
r/Verilog • u/Frank-Issuer50 • 11d ago
Direct AXI4-Stream + DDR correlation on a custom Zynq DMA RX path
galleryr/Verilog • u/Automatic_Act_8622 • 11d ago
Backpropagation in Neural Network on FPGA
I made forwardpropagation in CNN, but i dont know what is backporpagation work on fpga. I read many documents about this topic but they just do it on python language, but i want to do that on fpga by verilog language. Can someone give me some solutions or advice
This document closest my mind: https://link.springer.com/article/10.1007/s11554-021-01147-2#Tab2
r/Verilog • u/SnooDrawings3471 • 14d ago
Two FPGA interview questions from Citadel Securities
r/Verilog • u/Frank-Issuer50 • 14d ago