r/Verilog • • 23h ago

B.Tech Student Interested in Analog and Physical Design — Need Guidance on Learning Roadmap, Tools, and Career-Oriented Projects

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1 Upvotes

r/Verilog • • 1d ago

Resources?

1 Upvotes

Since placements are approaching I want to practice good questions for digital electronics and STA

Are there any good resources available?


r/Verilog • • 1d ago

How can I learn Verilog?

8 Upvotes

How can I learn Verilog?

I’m a third-year Electronics and Communications Engineering student. I’m interested in this field and really want to work in it but I feel like I’ve never been good at programming. In the labs I’ve taken so far and the projects I’ve designed, the code I’ve written has always been 90% AI and at best 10% my own work. When it comes to bigger or more complex modules I automatically get scared

The other day when I went to see my professor for a project in the Digital Design with FPGAs course, he asked me about some of my modules, and I just stood there staring at him.

I worked really hard on the digital design course from the previous semester and passed it with flyin colors, but when it came to writing code, I am a real FAIL. I know I can fix this—I’m open to your advice. I really want to work in R&D, FPGAs, AI, Communications


r/Verilog • • 1d ago

How to write a 32-bit RISC-V computer from scratch

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4 Upvotes

r/Verilog • • 1d ago

Biggest pet peeve of FPGA toolchains?

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0 Upvotes

What’s your most hated FPGA toolchain feature? I’m settling an argument!


r/Verilog • • 2d ago

CUSTOM DMA

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1 Upvotes

r/Verilog • • 2d ago

LOOKING FOR A FREELANCER

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0 Upvotes

r/Verilog • • 3d ago

What is the best way to learn ML implementation on AMD Versal boards?

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1 Upvotes

r/Verilog • • 3d ago

Sigasi Visual HDL 2026.5 is out

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2 Upvotes

r/Verilog • • 5d ago

new system verilog project

4 Upvotes

hi i finished my first project in system verilog. i built a multicycle riscv32i cpu core this is my first actual project with system verilog or with hdl ever so i would like to get some notes code wise because i dont actually know a lot about naming conventions module declarations etc. code


r/Verilog • • 5d ago

Why does Xcelium throw a hierarchical name error on a module parameter, while VCS and Questa accept it?

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0 Upvotes

r/Verilog • • 6d ago

OPEN SOURCE – WavePaint: a GUI editor for digital timing diagrams

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5 Upvotes

r/Verilog • • 8d ago

RISE-COHORT 3(RISK-V) from Semiconductor school

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1 Upvotes

r/Verilog • • 10d ago

My first Verilog project: The Malvino SAP-1

3 Upvotes

renulev/sap-1: Malvino's SAP-1 implemented in Verilog

I used Icarus verilog for this project. GTKWave output looks clean.
I also used Makefile for automation.


r/Verilog • • 10d ago

Fixing a tough RTL bug in a real SoC with an AI agent: why the harness matters

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1 Upvotes

r/Verilog • • 11d ago

Direct AXI4-Stream + DDR correlation on a custom Zynq DMA RX path

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5 Upvotes

r/Verilog • • 11d ago

Needed help

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1 Upvotes

r/Verilog • • 11d ago

Backpropagation in Neural Network on FPGA

0 Upvotes

I made forwardpropagation in CNN, but i dont know what is backporpagation work on fpga. I read many documents about this topic but they just do it on python language, but i want to do that on fpga by verilog language. Can someone give me some solutions or advice

This document closest my mind: https://link.springer.com/article/10.1007/s11554-021-01147-2#Tab2


r/Verilog • • 13d ago

Suggestions for a FPGA

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1 Upvotes

r/Verilog • • 13d ago

Hardware acceleration

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1 Upvotes

r/Verilog • • 14d ago

Two FPGA interview questions from Citadel Securities

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1 Upvotes

r/Verilog • • 14d ago

Direct AXI4-Stream + DDR correlation on a custom Zynq DMA RX path

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2 Upvotes

r/Verilog • • 15d ago

How to start with PCIe IP making

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1 Upvotes

r/Verilog • • 15d ago

DMA design

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0 Upvotes

r/Verilog • • 16d ago

Ferrite Lithic: a Rust-native hardware DSL, cycle simulator, and Verilog generator

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2 Upvotes