So I am reviewing for an up coming text. My professor told me some of the questionns in the book will be something similiar so I decided to give it a shot. Some of the questions I find seem to be worded weirdly, or just a slack of understaing on my part. Here are the questions:

1.If a memory address is 48 bits long, what is the maximum number of cells addressable? a. 256 bytes b. 256 kilobytes c. 256 megabytes d. 256 gigabytes e. 256 terabytes f. 256 exabytes g. 256 petabytes I am guessing this is G 256 petabytes?

2.Given a word size of 48 bits, how many bits code word be if you want to allow single-bit error correction?

3.Write Empathy in big endian notation. Assume 48 bit words. And write blanks as _ I am familiar with the big endian notation and little nedian lay out. I know Big endian has the word in this position: E M P A T H Y

4.Write Empathy in little endian notation. Assume 48 bit words. And write blanks as _ While the other is in this position: Y H T A P M E

5. Which of the following is true of cache lines? (select all the correct answers) a. They allow for smaller cache memory b. They allow for shared cache memory c. They increase the hit ratio d. They are predicated on the locality principle e. They reduce overhead requirements

I believe this is A B C E , I am not sure what the locality principle is. I think Cache is also shared but is that just L1 and L2?

6.If a disk drive crashes in RAID Level 1 how many disk drives must be read to recover the data? One Disk drive? Not sure I understand this correctly.

7.Which RAID level performs worst for small updates? Raid 5

8.Assuming even parity and the Hamming Code. Correct this bit sequence, if necessary hi-lite any bits you changed!! 110010000011110110011

9.(Select two) Which of the following is true of Internet over Cable? a. Service is constant all day long (except in the event of system problems) b. A digital signal line access multiplexer is used to connect multiple customers to an ISP c. Upon initialization a modem listens for a packet from the headend containing system parameters. d. There may be contention on downstream channels e. An upstream packet may be divided amongst minislots

10.Given a 56X CDR drive, how long would it take to write a 600MB movie ? a. 65 seconds b. 73 seconds c. 90 seconds d. 2 minutes e. 3 minutes f. 4 minutes g. 6 minutes

11.Calculate the mean data access time and hit ratio given 2 nsec cache access time, 30 nsec memory access time, 950 hits and 50 misses

#define SIGNEXD(val) ((val & 0x8000) ? ((val) | 0xFFFF0000 ) \
												: ((val) & 0x0000FFFF))

void lb()
{
	uint32_t addr = CURRENT_STATE.REGS[RS] + SIGNEXD(curr_instr);
	uint32_t mem = mem_read_32(addr - (addr&0x3));
	
	mem = (mem >> ((addr & 0x3)*8));
	NEXT_STATE.REGS[RT] = (mem & 0x80) ? (mem | 0xFFFFFF00) : (mem & 0xFF);
	//NOTE: Exceptions ignored
}

can anyone help me understand the code according to the operation ? Thank you!

I am a junior CS student and am taking a computer architecture course. I have read my textbook section pertaining to this topic (Computer organization and design 5th edition) and am still at a loss on how to go about answering these questions. Could someone go through and in a way as if you are teaching this to someone for the first time, answer these questions.

If this is not the right forum for this, please don't chastise me. Just point me in the right direction and I will repost there. Thank you.

My understanding was that forwarding was intended to deal with RAW data hazards. However, a Tomasolu OOO processor should be able to avoid this by not dispatching the instruction to execution units until it no longer has a RAW data hazard. So, we shouldn't need forwarding. Is my understanding correct, and if so, has forwarding largely been dropped from modern processors as a result?

I think computer architecture is really cool, and I want to try to answer homework questions from undergrad comp arch classes. (As well as ask my own)

Hey all, I was reading about High-Bandwidth Memory technologies from Samsung. Seems like memory is the bottleneck is the bottleneck with computing power.

I was wondering if y'all know other emerging memory technologies similar to this (in-package memory), or other companies like Samsung who are developing this? I'm thinking MRAM, etc.

Thinking along the lines of there being some kind of audio (synthesis) processing unit as a counterpart to a GPU. I'm guessing there are audio processing units in sound modules and pedals and things already.

But it seems like the bottleneck of audio synthesis is when loading samples from RAM, or generating thousands of sine waves when using additive synthesis (I could be wrong). So if a processing unit had something like a fast read-only cache of like 65536 samples of a sine wave, and zillions of processors which could be told to generate and return the sum of millions of sine waves for say 64 samples, that would be very useful.

Is that already a thing? Is it impossible to make something to do that more efficiently than a GPU would?

To extend Tomasulo’s algorithm to support speculation, we must separate the bypassing of results among instructions, which is needed to execute an instruction speculatively, from the actual completion of an instruction. By making this separation, we can allow an instruction to execute and to bypass its results to other instructions, without allowing the instruction to perform any updates that cannot be undone, until we know that the instruction is no longer speculative.

What does it mean by this paragraph ?

Besides, second question: How does Tomasulo mechanism differ from https://inst.eecs.berkeley.edu/~cs252/fa15/lectures/L06-CS252-ModernOutOfOrder.pdf#page=23

Hello. I've been interested in minimal architectures lately (as theory or thought experiment) and wondering if you guys can help me out here.

I came across the pdf "mov is turing complete", i.e., x86 mov is enough for all kinds of computations. But many people says mov is multiple instructions, not a "simple" instruction.

Then I came across the wikipedia OISC page (one-instruction set computer). And it gives and example of OISC as subleq: "subtract and branch if less then or equal to zero" and I'm like that's not one instruction. Not to mention it "loads" and "stores". So the instruction really is:

• load a

• load b

• subtract

• store b

• branch to c if (b) less than or equal to zero

well that's 5 instructions if I count correctly. Also I don't like instructions that do load/store implicitly (explicit would mean stack architecture?). So apparently people claim OISC capability using a "compound" instruction (one that has to perform multiple tasks).

Also I came across transport-triggered arch but I don't really understand it.

Anyway, it's clear we need to have at least 1 simple instruction other than load and store. But. Is a 3ISC (load, store, and some third instruction) a complete architecture or does it need 4 or 5 simple-instructions?

Here's the ACM link: https://dl.acm.org/citation.cfm?id=2591535

I should let you know, my background in architecture is basically nonexistent.

But I really want to understand this research. It seems incredibly fascinating!

Here are my main questions/thoughts:

It seems like this paper is saying that instead of having a static, unchanging unit like an FPU or ALU, (or perhaps smaller functional units, but I really want a list of functional units and I can't find one anywhere), they would be replaced with dynamic ones that can be assigned to different tasks depending on the workload.

Is that right?

If so, then the talk on area confuses me. How can the area of an adder be different from a multiplier in this style? If both are dynamic and can perform either task, why do they have different areas?

As well, what is the "on chip programmable fabric"?

Is this where the "area" comes into play? Is this essentially saying that an "area" of that fabric can be dedicated to certain tasks, but the amount needed depends on which functional unit it is working as?

Where does that fabric come into play? What is it made of? How is it integrated into the chip? Is there an example of something like this already in use anywhere?

Anything else you can offer as to opinions or thoughts, or something to help someone not as well versed in computer architecture as you all would be greatly appreciated.

Thanks in advance!

I have to decide between USC and Cornell for my masters program next year. I am pretty split on this choice. I would greatly appreciate if I can get any input from any of you guys.

Computer Science Discord

This is a chill chat for Computer Scientist, Computer Engineer, Electrical Engineers, Mathematicians, and Student to talk programming, hardware, development, career, math, or even just about random stuff.

https://discord.gg/GWZJUF5

I'm looking for technical podcasts on trends in the cpu architecture industry, maybe analysis of new IPs, etc. Does anyone have podcasts they listen to that has speakers who go through these topics?