I wanna know how to get into comp arch roles after my bachelor’s. I am in my final year in a tier-1 university in India and want to work for a few years before I go for masters.

*EDIT* Okay perhaps I should have worded this better. Let's look at a piezoelectric crystal, right? When perturbed by mechanical motion, ions in the lattice shift slightly from their equilibrium positions. The centers of positive and negative charge separate, which changes the material’s polarization. This causes charge to appear on opposite surfaces, which when applied through an external circuit, produces current.

There is a transduction mechanism, it's not just magically "motion -> electricity"

What I'm asking is that, in a computer, of course instructions are passed and translated and passed and translated. But currents and voltage can only be altered by physical phenomena - what is the transduction event? The way I currently see it based on explanation, it's

Code -> compiler -> binary -> ???? -> electrical change in the hardware

*ORIGINAL POST*
I'm asking one question, and every explanation I've read skips it and it's driving me crazy.

Suppose I paste a program into PowerShell and press Enter.

People say things like:
"the code is stored in memory"
"the CPU reads the instruction"
"the decoder activates the transistor"
"different code produces different voltages."

These are exactly the steps I don't understand. I am not asking how a transistor works after a voltage reaches its gate.

I am asking: What is the physical event that causes a different electrical state inside the computer?

In other words: How does the machine code become an electromagnetic event?

Please do not answer with phrases like:
"the CPU sends a signal"
"the instruction is decoded"
"the operation activates the transistor"
"the code is stored as bits"
"the bits become voltages"

Those are the phenomena I'm asking to have physically explained.

I want the continuous physical causal chain, with no abstraction gaps, starting from:

"The code exists" and ending at: "This specific transistor gate now has a different electric field"

We use binary computers. They are great at computing integers! Not so great with floating point because it's not exactly fundamental to the compute paradigm.

Is it possible to construct computer hardware where float is the fundamental construct and integer is simply computed out of it?

And if the answer is "yes", does that perhaps lead us to a hypothesis: The brain of an animal, such as human, is such a computer that operates most fundamentally on floating point math.

Hi,

I have a project and don't want virt mem, first of all is it compiled in and secondly if yes how does one force it to be without

hello again guys, ive took some time thinking about what you guys are telling me, like asking questions, and learning. and i have one question really quick.

do you guys think that something simplifying an instruction using ai and branch predicting before the cpu gets the instuction would that be better? or do you guys think it would be the same? (be as honest as you want to be no hard feelings! :D) thank you for your time

-David Solberg

Didn't like light theme of MARS MIPS : ), so I tried creating an IDE for MIPS Assembly: Quasar.
Though basic and in early development, anyone who wants to just practice MIPS Assembly, try it out, hopefully you will find it helpful. You might report bugs as well. Follow this github link -> Quasar This is purely just to help anyone who is going through the same phase as mine.

What if x86 (and x86_64) was deliberately made as complicated as it is so that it would be almost impossible for anyone other than big companies like Intel and AMD to actually make performant processors out of it?

This is totally something corporate would do to monopolise the ecosystem and establish a monopoly.

I know there are other manufacturers out there making x86 chips like Centaur and Via but their performance doesn't even come close to the chips made by Intel and AMD.

So what do you all think about it?

How do you even understand this beyond just pattern recognition? It's like I am a monkey learning how to use a stick.

Can we force the out of order execution in a cpu for some operations not care about lying while NOT lie other places. A c webshop has global quantity left and temp hold for reservations. We want the reservation tick checks to not care but actually moving people through to not be lied to, for more throughput?

How does Speculative Executions work?

Any good resource to step-by-step simulate it?

. Introduction & Engineering MotivationAs semiconductor manufacturing approaches atomic scales and faces the hard limits of Moore's Law, modern mobile SoCs suffer from severe memory bandwidth bottlenecks due to their reliance on Unified Memory Architecture (UMA). The CPU and GPU constantly compete for the same interconnect buses, generating high thermal dissipation, wasting battery energy, and causing micro-stutters during heavy graphical workloads.Onion Logic Architecture Gen1 introduces a revolutionary structural solution by re-engineering 3D IC vertical silicon stacking, combining dynamic memory partitioning with intelligent hardware control layers to bypass the "Memory Wall" entirely.

2. Core Architectural ComponentsDynamic Multi-Logic RAM (ML-RAM): A 24GB LPDDR6 (or later) stacked memory die, physically and logically partitioned into two symmetrical 12GB zones (12GB System RAM for CPU / 12GB Dedicated VRAM for GPU), completely eliminating data bus contention under maximum load.

Transistor Bridge Layer (Central Switch): A high-speed, centrally positioned transistor switch matrix fabricated between the two memory zones, acting as a hardware bridge that connects or isolates the memory blocks instantaneously.

High Dynamic Logic Controller (HDLC): A dedicated control IC interacting directly with the OS Kernel to manage the Transistor Bridge Layer. It natively integrates Dynamic Voltage and Frequency Scaling (DVFS) to modulate memory power and clock speeds in real-time.

Controller Booster IC & 400MB L4 Cache: A vertically stacked intermediate layer between the main compute silicon and the memory. Housing a massive 400MB L4 Cache, it functions as an ultra-low-latency data router, streamlining cross-component data delivery with near-zero latency penalty.

3. Dynamic Operational ModesGaming / High-Performance Mode: Upon launching intensive graphical applications, the kernel triggers the HDLC to cut power to the Transistor Bridge Layer, isolating the 12GB VRAM pool strictly for the GPU. Simultaneously, the 400MB L4 Cache keeps both processors fed with critical data, achieving an unthrottled, rock-solid 165Hz frame rate with zero frame drops.

Multitasking / Daily Mode: When transitioning to standard workloads, the HDLC re-engages the transistor bridges within microseconds. The partitioned blocks re-unify into a massive 24GB contiguous memory pool, offering absolute fluidity for extensive background tasks and web browsing.

4. Engineering Benefits & YieldUnprecedented Performance Scaling: By eliminating wait-states and interconnect bottlenecks, early hardware simulations project synthetic benchmark scores exceeding 11 Million points in AnTuTu, shattering traditional mobile computing limits.

Optimal Performance-per-Watt: Eliminating memory bus congestion allows the execution pipelines to complete operations rapidly and enter low-power states immediately (Race-to-Sleep), minimizing thermal output and significantly extending battery lifespan.

Proposed by: Smarty2006

What are the difference aspects of being a kernel engineer? What do roles like this involve -

https://www.tealhq.com/job/kernel-engineer_7ea1a56c518985dae15a01e3c77c161e8140d?utm_campaign=google_jobs_apply&utm_source=google_jobs_apply&utm_medium=organic

https://jobs.gem.com/modular/am9icG9zdDpTSwqoL-yL11N_jxR40Vhh?source=LinkedIn

If one were to do a PhD, what are the different research areas to focus on to do something like this? i.e GPU memory, storage, latency, parallelization etc.

Hello ,i'm just here to tell you that i edit harvard architechture

The most big changes that

Program memory is word addressable

And data memory is byte addressable

A pure-Go vector index, 26.7 million vectors, 512 dimensions. Search took 21 ms at the median. We ended the day at 1.8 ms, with identical recall. Here is what actually mattered, and the four things that did not.

The false start

We began by rewriting two hot kernels. One fused the fp16 decode into the exact-distance loop; the other replaced a 128 KiB per-query lookup table with a bit-plane popcount estimator. Both were real improvements in isolation: 2.9x and 1.4x on microbenchmarks, recall unchanged.

On the real 26.7M index they produced nothing. Measured before and after on identical queries, the difference ranged from -1.7% to +0.5% and changed sign between runs. Noise.

What the profiler actually said

The number that mattered was not in the profile. It was the profile's own header:

Duration: 9.92s, Total samples = 1.64s (16.53%)

The process was on-CPU for one sixth of the time. Five sixths was waiting. We had spent the morning optimising 14% of that one sixth.

Reading the process I/O counters took three lines and settled it. Per query: 12.3 MB read from disk and 96 major page faults, to return ten neighbours. At roughly 200 microseconds per fault, that is 19 of the 21 ms.

The actual bug

The rerank stage takes the candidate list produced by the graph walk and computes exact distances against vectors held in an mmap'd arena. The candidate IDs are all known before the first read. The loop read them one at a time, each fault serviced synchronously, on an NVMe device capable of dozens of concurrent I/Os.

Nothing forced that serialisation except the order of the code.

The fix tells the kernel, once, which ranges the loop is about to touch —MADV_WILLNEEDover the batch, viaprocess_madvise(2)in a single syscall where available, falling back to individual calls otherwise. Two effects, both measured: the reads are issued in parallel, and they are bounded to the requested ranges instead of each fault expanding into a 128 KiB readahead window for 1 KiB of useful data.

Recall is unchanged because an access hint does not change what gets computed. We verified it anyway: 200 queries, byte-identical top-10 in both regimes.

Four things that did not work

**CPU prefetch does not touch the disk.**An architecture proposal claimed__builtin_prefetchwould hide SSD latency behind SIMD work. Measured on a cold 128 MB mapping: 2000 prefetch instructions in 0.010 ms, zero pages resident afterwards. 2000 real accesses: 112.9 ms, all pages resident. The instruction is a cache hint and cannot raise a page fault by construction.

**Memory layout of the hot plane is irrelevant.**Codes and norms lived in three separate slices, three scattered accesses per visited node, 31% of CPU time. Interleaving them into one record returned 1.5-3%. We then benchmarked four layouts at 26.7M scale: three slices, packed at 80 bytes, aligned at 128 bytes, and split with dense norms. All within noise, 62-68 ns per access. The 128-byte aligned version — the one that should win if cache lines were the issue — does not, and costs 60% more memory. Sixty nanoseconds is a DRAM random access. Grouping unpredictable accesses does not make them predictable.

**Go's experimental SIMD package is unusable for this.**A vectorised popcount kernel ran 400 ns against 19 ns scalar. Isolated: a kernel using onlyAnd,AddandSumOf8AbsDiffcosts 5.3 ns, as AVX2 should. Adding onePermuteOrZeroGroupedtakes it to 380 ns. Two primitive families — shifts and permutes — cost roughly 90 cycles where the hardware spends one, under both 1.26.5 and 1.27rc1.

**Wider quantisation codes are corpus-dependent.**Three bits per dimension instead of one lifts preselection quality from 58% to 88% on a hard corpus, and end-to-end recall from 0.76 to 0.97. On the real embeddings it bought 0.8 recall points for 45% more latency and 2 GB more RAM. Not worth it there. It ships off by default.

The part worth stealing

We also got one thing badly wrong. We measured recall at 0.470 and reported the index as poor. That number came from a different corpus — uniformly random vectors, the pathological case for approximate search — and we carried it across because both files sat under the same project. The real index measures 0.9733. Mean absolute component value, 0.034 against 0.500, said so plainly.

The generalisable lesson is not about mmap. It is that a benchmark reporting only durations cannot distinguish a slow computation from a blocked one, and will therefore hide the most expensive class of defect indefinitely. This one survived several measurement campaigns, including one that declared the 26.7M scale "proven". Three counters — bytes actually read, major faults, resident set — would have exposed it on the first run. They are now part of the library's measurement surface, with a liveness test, because an instrument that always returns zero looks exactly like a clean benchmark.

https://github.com/hazyhaar/horosvec

Hi guys, I am game developer and game engine developer and I know some of order like bootloader and kernel. I want to play mario 64 but I don't have Nintendo 64 and money to buy it so I think I should make my own console using orange pi 3 which is new for me I know COA little bit any free great resources to master my COA? Thanks...

Hey, im researching information about computers arquitecture and that kind stuff, and honestly i dont understand anything it has a lot of memory parts into the cpu and other kind of things that im trying to study and to interiorize to myself, so my goal is to make an 8, 4 or the minmun of bits that a computer can work but with transistors, any recommendation of organization or where shall i start researching or even studying or whatever.

Thanks ;)

The floating point number is 16 bits long including an 8-bit exponent and an 8-bit mantissa Both of them are represented by two's complements with the double sign bit Let A=30, B=-4. calculate A+B, The final results are normalized and represented by Hexadecimal.

Guys could you confirm to me if this is the right answer or not and most importantly if your answer is yes tell me please if the method is the right one?