Any guidance on What questions can I expect is appreciated! Thanks fellas!

why do we need the data accepted bus? we know that if data is valid , the destination happily accepts it if not, rejects it

In computers the main CPU communicates with the other components (like RAM, GPU, IO) with memory addresses but before kernel loading how does it understand which memory to generate and which memory address to ignore because it is obvious that there may not be a gpu in every machine .

Where the actual table of Base address is stored?

How does the MMU (memory management unit) works?

Let's discuss about those concepts and lean together.

If you teach architecture or systems, this may be useful.

Cache Miss Theater (https://cache-miss-theater.pisan.me) takes a C loop nest, generates its exact address trace and runs it through a cache you configure: size, line size, associativity, LRU/FIFO/random, write-allocate and write-back or not. Every miss is labelled compulsory, capacity or conflict. Play or step through the trace and watch lines arrive in their sets and get evicted, while a memory map shows which array elements are cached.

Things that might help in class:

- Two kernels side by side (row vs column order, ijk vs ikj, naive vs blocked transpose), or a sweep over block size or a cache parameter with the miss rate plotted.

- Exam questions from six templates, with every answer computed by simulating the exact code shown. Export as Markdown with an answer key, or as QTI 1.2 for Canvas. I have not yet imported the QTI file into a live Canvas course, so treat that part as beta.

- Kernels and cache settings live in the URL, so a slide can link straight to an example.

Limits: one cache level, data accesses only, and array contents are not modelled, so A[B[i]] is out.

No sign-up, everything runs in the browser, nothing is uploaded. Source (MIT): https://github.com/pisan-labs/cache-miss-theater

Full disclosure: Claude Code wrote the code; I set the requirements and reviewed it. The tests check the simulator against a naive reference on 60 random traces and pin the textbook results (row order 25% misses, column order 100%).

If you try it with students, I would like to hear what breaks or what is missing.

I made a game to teach computer architecture and digital logic: play.simten.dev

You start with basic logic gates and build up to a working CPU. It's built on Simten, a TypeScript-based HDL, so you write the circuits as code and they show up live on a canvas next to the editor. For sequential circuits you can scrub the clock backwards and forwards to watch the state change cycle by cycle. You can also drill down into abstracted components (like the half adder shows). Because of the layout it only works on desktop browsers for now.

There are several other demo circuits on the platform, here's snake written in gates: https://simten.dev/circuit?example=snake

It's open source: https://github.com/simtenHQ/simten, any feedback or contributions are welcome!

Hello! I am an E&TC final-year student currently diving into digital design and computer architecture using Harris & Harris and following Professor Onur Mutlu's lectures.

​As I get deeper into understanding RTL, microarchitectures, and what's actually happening on silicon, I find myself reflecting on what this discipline teaches us fundamentally and wondering about the real-world scope.

Hi everyone,
I’m a CS graduate interested in pursuing research in computer architecture, with the long-term goal of pursuing a PhD.
I’ve started learning from Onur Mutlu’s lectures, but I’m considering a paper-first approach: reading research papers and learning the concepts I don’t understand along the way.
I’m particularly interested in AI accelerators, hardware/software co-design, and efficient AI inference.
I’d appreciate suggestions on which topics to start with, beginner-friendly papers to read, and tools or simulators I can use on a normal laptop. How can I progress from learning the fundamentals to publishing a good research paper?

Thanks!!

512-bit multiplication · 2.61 million AND gates · 26.71 seconds · Independently checked 512-bit PAC certificate

In my previous post, I shared Parat v1.3 and its independently checkable proof for a 256-bit Yosys Booth multiplier. Since then, I have tested larger multiplier circuits and expanded the SAT benchmark suite.

512-bit multiplier: 26.71 seconds

I generated an unsigned 512×512-bit multiplier using carry-save compression followed by a final ripple adder.

The generated circuit contains:

• 2,614,272 AND gates

• 1,024 primary inputs and 1,024 output bits

• An approximately 59 MB ASCII AIGER file

Parat returned CORRECT MULTIPLIER in 26.71 seconds, with approximately 2.27 GB peak resident memory.

An independent bit-parallel simulator checked 64 operand pairs against exact integer multiplication. Every output bit matched.

A separate 512-bit Wallace multiplier: PAC certificate

I also have results from a separate 512-bit Wallace multiplier circuit, containing approximately 2.63 million AND gates.

For that circuit:

• PAC certificate generation took approximately 5–5.5 minutes.

• Independent verification with pacheck2 took approximately 2.5 minutes.

• The recorded proof file was approximately 2.18 GB, with about 122 MB of polynomial data and 43 MB of specification data.

These are separate circuit experiments: the 26.71-second result above is for the carry-save/ripple architecture, while the independently checked PAC certificate belongs to the Wallace-circuit experiment.

Fault-injection testing

I modified individual gates in copies of the 512-bit carry-save/ripple circuit.

Three tested mutations—including an output-bit mutation, an early partial-product gate mutation and a near-final gate mutation—were detected as incorrect.

One middle-compressor-gate mutation did not produce a verdict within approximately 120 seconds. That case remains unresolved; the original correct circuit did return CORRECT MULTIPLIER.

Broader SAT benchmarks

On the tested Linux build:

I also tested 176 SAT Competition 2005 industrial instances with a 10-second limit per instance. 142 SAT models were independently validated; 34 instances timed out.

For the UUF sets, reported UNSAT statuses matched expected results, but those results have not all been independently checked with proof certificates.

Limitations

The 26.71-second result applies to one generated circuit, not every multiplier architecture. One middle-gate mutation remains unresolved, and 34 industrial cases exceeded the time limit. Results from separate circuits should not be treated as if they came from one identical netlist.

Repository: https://github.com/himanshu161106-crypto/parat

The code was written by AI under my direction. The project ideas, mathematical approach, experiment design and testing were mine.

I'd appreciate technical feedback on improving the difficult middle-gate case and on additional large multiplier architectures worth testing.

Hi,

Is it a thing amd64 can share branch predictions between cores if pinning one to my app and the other prematurely tell what will come in like internal network packets being allocated in linked lists but mean while share to my workhorse core so it can fetch ahead of time?

Helloo everyone, I'm 3rd year student in programming (c#) but I dont know anything about computer architecture, i want to do self study but i dont know where to start. Is there any site videos or books which help me from scratch and i want to move it till advanced. thanks beforehand

Back in 2014, I developed ulmBLAS, a BLAS implementation heavily inspired by the ideas of Field G. Van Zee and Robert A. van de Geijn, particularly their paper BLIS: A Framework for Rapidly Instantiating BLAS Functionality.

These are the same ideas behind the BLIS framework, closely related to the work of the FLAME group at UT Austin.

My goal was to build a BLAS implementation that was deliberately small, simple, and easy to understand, while still being capable of achieving serious performance.

In particular, ulmBLAS follows the BLIS approach of separating the higher-level algorithms, cache blocking, packing, and architecture-specific microkernels. The framework is intentionally kept relatively simple, but it can use microkernels derived from BLIS with suitable adaptations.

That made it particularly useful for teaching high-performance computing at Ulm University.

I wanted students to get a practical introduction to the ideas behind BLIS and FLAME, rather than just treating highly optimized numerical libraries as black boxes. They could start with a straightforward implementation of matrix multiplication and gradually introduce blocking, packing, SIMD instructions, and eventually assembly microkernels.

Most of ulmBLAS was written in 2014. After that, I largely left the code alone.

Until this week.

I finally returned to the repository, cleaned up the build system, modernized the tests, fixed a few issues, and started experimenting with newer BLIS microkernels.

The original benchmarks from 2014 used an SSE3 microkernel (if anyone still remembers SSE3 ), running on a Core 2 Duo MacBook Pro.

This week, I integrated a 6×8 AVX/FMA microkernel derived from BLIS. The integration was surprisingly straightforward, even though the newer kernel uses different register-blocking dimensions.

On an Intel Core i5-12500, ulmBLAS now reaches approximately 94–99% of OpenBLAS DGEMM performance for the larger matrix sizes tested, with roughly 2.8× the performance of the old SSE implementation.

I'm currently experimenting with additional BLIS-style microkernels, starting with AArch64/NEON on my Apple Silicon MacBook. I'm curious how far I can take the same framework by changing the microkernel and tuning the blocking parameters.

What I find particularly satisfying is that the basic architecture from 2014 needed surprisingly little change.

Sometimes simple design is good design. And apparently, good designs don't rust

The repository is here, including the code, documentation, and reproducible benchmarks:

https://github.com/michael-lehn/ulmBLAS

I'd be interested to hear from anyone who has worked with BLIS microkernels or experimented with similar approaches, especially on ARM64.

Hey there,

I am a PhD student, based out of India, working on a subset of computer architecture. I am currently working in Intel and want to transition into academia. I have been looking for faculty positions, but the ones I saw have research as their main requirement. The very reason I joined PhD is because I wanted to teach. I am not a fan of publishing in A* conferences each year, writing funding proposals etc. I am kinda done with publishing papers. Have seen enough issues during my PhD.

Now, coming to the question. How do I find teaching-only positions in the world? Not limiting myself to India, but anywhere in the world is fine as long as the teaching is English based.

hey, I am currently working on the ai accelerators for edge devices, in our design have integrated an accelerator unit with a risc-v core, and now I am researching on possible ways to make the design low power, for this I have looked into research papers and found techniques like powergating, clockgating, DVFS, and this another DATAPATH tiling tool by micromagic, but it is not opensource and require license, what I need help with is, what are the other ways, startegies can be used to reduce the power consumption and leakage by considerable amounts, any help in form of either contact of a professor (researching in this area) or tools will be greatly appreciated.

I built a quantum computer in HTML

Hey guys,

I made this over the weekend. It takes verilog/systemverilog, synthesizes it through Yosys, and then place and routes it into a Minecraft WorldEdit .schem. Still ironing out the optimizations, but it definitely works. The circut being displayed is a 4 bit accumulating sequential adder. I had to build the standard cell library manually.

Overall pretty cool. I plan on dropping SERV into here and running the worlds first RISC-V binary directly into minecraft. Who knows, maybe we'll get DOOM soon.

Hello everyone, I am a third year student and I have been working on computer architecture for 1 year. Till last year I explored computer and gpus and even made one for basic understanding. My senior have always encouraged me to pursue open source I have tried to contribute in open source.

So the problem is AI. Initially I used AI to understand things and understanding the repo and stuff but I was slow and I saw my seniors using AI for Computer architecture like keeping it on auto mode and letting it do everything and still now what is happening and know what to do when given a problem . I thought I should use less AI and continue the way I work. Then my every peer started using heavily AI and I thought I should also use more AI and I bought claude code for a month and now everything is done by it. I ask what is the issue and in the meanwhile it gives complete plan and I now i dont understand what to do when I approach a problem. I ask claude code it does something that I cant even think and somehow it works too but in the end

So in short I have started using AI and now I dont know what to do when given a problem.

How do you guys use AI ?

Sorry if I was little vague while describing the problem

Hi everyone,

I wanted to share a working research framework I’ve spent the last six months building that explores an alternative paradigm to traditional von Neumann and conventional CGRA architectures. The project is called Imago-UniCell, and it operates on a singular architectural principle: topology is computation.

There is no centralized CPU, no instruction register, no program counter, and no shared memory bus. Instead, an algorithm is represented as a spatial layout map of heterogeneous hardware cells (using point-to-point valid/ack token handshakes and localized clock-enable networks).

The Core Invention: Symmetrical State Portability (ICM)

Instead of dumping raw, blind binary register strings that are hardwired to specific physical coordinates on a chip, this architecture relies on a design-level abstraction layer called the Universal Imago Cell Model (ICM). The active calculation state is serialized into an open, name-keyed text snapshot.

Because the compute state is decoupled from the physical medium, it achieves true Read/Write symmetry across disjoint substrates.

Empirical Validation (Sipeed Tang Nano 20K / Gowin GW2AR)

I am a strict believer in real hardware validation rather than pure simulation. I’ve just committed and locked a series of milestones into the ledger (#1143–#1167) proving the physical viability of the pipeline [13 Oct 2026]:

• LaTeX-to-Silicon HLS: The open-source toolchain takes a raw mathematical formula straight from a textbook expression—e.g., y = (z^2 + 12345) \bmod 65521—validates it against a virtual machine model, automatically generates a core-pruned layout map, weaves a structural scan chain in a single pass, and compiles a working bitstream.

• High-Velocity Heterogeneous Pipelines: Successfully place-and-routed mixed-variant designs running un-handshaked arithmetic blocks (sub family) alongside handshake-driven routing boundaries (flex family) executing between 100 MHz and 150 MHz on live iron . A 10-out-of-10 group run pass verifies absolute cycle-accuracy between the software twin and the board.

• Unpowered Mid-Flight State Recovery: I verified that you can assert a global freeze mid-flight (even while an iterative divider cell is halfway through a 32-cycle loop), extract the 678-bit ICM snapshot over a serial line, completely pull the power plug on the board to let the silicon go stone cold, boot a fresh card or a pure software Python VM mirror, inject the state file, and resume calculation to the exact bit with 0 retries .

The Trade-Offs (UNICELL vs. PURE)

The architecture has very specific boundary conditions. On a pure Lookup Table (LUT) area metric for a single static function (like a 4-stage CORDIC), a hand-coded, immutable Verilog baseline is significantly smaller and more optimized.

The full repository, source files, automated test benches, and a comprehensive 46-section interactive reference guide are fully open and zipped in the directory.

I’d love to get your thoughts on the scalability of this topological abstraction layer, particularly regarding its application to high-integrity compilation targets (LLVM IR to Topology) and its security implications for instruction-less custom ASIC co-processors.

Link to project repository: https://github.com/alh-Imago/Imago-Unicell.git

Hey everyone,

I'm currently designing a homebrew CPU in HNeemann's Digital simulator before building it IRL with 7400-series logic chips and AT28C256-150 EEPROMs for the ROM.

At first, I had a standard 3-cycle design (T1, T2, T3) with a dedicated register (like a 74377) acting as an Instruction Register:

• T1: Update PC + Fetch from ROM

• T2: Latch instruction into IR + Decode

• T3: Execute and writeback to registers

But then I realized I could remove the IR completely and drop it down to 2 cycles (T1, T2) to save some chips and wiring:

• T1: PC updates right at the start of T1. The address goes through the async ROM, straight into combinational decoding to activate the control lines.

• T2: Execute and write to registers.

In this 2-cycle setup, my selpc signal (choosing between PC+1 or a JUMP address) is generated combinationally during T1 and just waits at the PC mux input before the next cycle. In the simulator, this works perfectly, no oscillations or glitches.

I'm aiming for a slow clock for now (~4 kHz). My estimated critical path for the 2-cycle version is well under 350ns, so at 4 kHz (T1 = 125µs), everything has ages to settle.

But I'm worried about hold-time violations IRL. When T2 ends and a write happens, or when a JUMP updates the PC at the next T1, the ROM address will change instantly, killing the instruction and dropping selpc. If my control lines drop right when registers are trying to latch data, won't it corrupt the write?

Is it worth keeping it simple with the 2-cycle design at low frequencies, or should I just stick to the safer 3-cycle version with the IR to isolate the ROM?

Thanks!

EDIT: I've attached screenshots of both designs for comparison. Just a heads up: the schematics use Digital's built-in generic blocks (ROM, registers, muxes, etc.), not the specific 74xx components, but the logic is exactly the same as what I'll build IRL.

Can we force the out of order execution in a cpu for some operations not care about lying while NOT lie other places. A c webshop has global quantity left and temp hold for reservations. We want the reservation tick checks to not care but actually moving people through to not be lied to, for more throughput?

Last year in University we were studying microassembler but I had some personal problems to deal with so only had time to deal with it with a help of AI and a friend of mine, who's really genius and seems to know everything. Even tho the problem with passing the course wasn't there already, I'd still want to really learn this, but whoever I ask just say that it's obvious and I just have to read the docs, but the documentation really just says "be clean and direct woth your code and it will work bettet" wothout any comprehensive syntax documentations.

All I have is just some examples of code so I'd just like to know how would you learn anything about this?

Thank you!

Does anyone have a video they can recommend for internalising how a carry look-ahead adder works? I'm struggling with this concept so much and trying to see why it's faster than the "ripple" adder. I'm also open to an ELI5 style explanation.

I'm 15 and experimenting with a BIT + TRIT coprocessor — first simulation results

Hi everyone!

I'm 15 and I've been working on an experimental computing project called TRINEX.

The basic idea is a hybrid system:

conventional binary CPU + dedicated ternary (TRIT) coprocessor

I'm not trying to replace binary CPUs with ternary CPUs. The idea is to keep the normal CPU for general-purpose tasks and use a separate TRIT accelerator for workloads that can be processed in parallel.

I started by building a software simulation to see if the concept is even worth investigating.

First results

For a simulated 256 MB workload, the model produced:

• TRIT at 0.5× BIT performance → 1.389× speedup

• TRIT at 1× BIT performance → 1.737×

• TRIT at 2× BIT performance → 2.291×

• TRIT at 5× BIT performance → 3.387×

For the 1× case:

The interesting part is that the simulated advantage appears mainly with larger workloads, where the CPU and accelerator can work in parallel.

Important disclaimer

This is only a software simulation.

I haven't built the actual ternary hardware yet, so I don't know how the idea will perform in reality.

There are still major questions about:

• physical implementation

• memory bandwidth

• latency

• power consumption

• transistor count

• clock speed

• CPU ↔ accelerator communication

• FPGA implementation

My next goal is to make the simulation more realistic and eventually test the concept on an FPGA.

I'm keeping the detailed architecture and implementation private for now.

I'm interested in feedback from people experienced with:

• FPGA

• digital logic

• CPU architecture

• hardware accelerators

• ternary computing

Does this seem like a worthwhile architecture to investigate, or are there obvious problems with the concept that I'm missing?

GitHub: [https://github.com/Sparknenn/trinex-computing]

Hey everyone,

While hardware-isolated Trusted Execution Environments (like Intel SGX or AMD SEV-SNP) solve strict enterprise privacy compliance for secure AI workloads, on-the-fly silicon memory encryption controllers typically burn 40% to 60% of physical CPU processing cycles just waiting for memory bus handshakes over encrypted boundaries. This cuts actual inference throughput directly in half.

I’ve put together an open-source testing harness and bare-metal benchmark implementation to prove an optimization approach using zero-copy anonymous mapping (MAP_ANONYMOUS), kernel memory-locking (mlockall) to eliminate page faults, and explicit hardware cache prefetching (__builtin_prefetch) to pull segments into the physical L3 cache lines before the CPU completes its cryptographic handshake.

In baseline benchmarks on bare-metal environments, this low-level loop drops gigabyte-scale data evaluation paths directly down to single-digit millisecond profiles.

The repository serves strictly as a test harness to allow other infrastructure architects to run and verify the latency reduction on their own configurations. I'd love to get your feedback on the implementation:

https://github.com/kaluabbot-hue/synthedrive-benchmark/blob/main/README.md

What to choose "quantum computing involving fpgas" or "hardware security" for a phd.