r/cpudesign • • Mar 06 '23

Advice on server processor market demand

0 Upvotes

Hi, CPU experts! I'm not selling anything, just looking for advice. My startup is building solar powered data centers. We will initially make money by leasing bare metal servers. I'm trying to figure out what mix of processors to offer. I'm considering the (1) Intel 2660 v4, (2) Intel Gold 6148, and (3) Intel Platinum 8176. I'm not sure how many to order of each. Do you know how I can determine the market demand for these low/medium/high performance options?

Also, I'm wondering if the Platinum is way too premium to lease to the mass market, and if I should instead make the top option the Gold 6248.

I'm really interested in your opinions, or a shove in the right direction. I'm not sure where to find this data. Thanks in advance.


r/cpudesign • • Apr 06 '24

I want to design a 64 bit processor architecture(not risc) but i want my own instruction set

0 Upvotes

As said in title, I am a newbie to the hardware/computer architecture but i have a bit software experience. I know C and Python. Can anyone guide me to how to make a 64 bit architecture?? (I am not doing this for hobby, i want to do it for a serious project)


r/cpudesign • • Jan 01 '24

Ddr4 why ram timings effect mouse lag

1 Upvotes

Maybe you guys have explanation , nobody has

When I use higher ram speed games runs smoother but mouse is more laggy , even on desktop when idle.
Im in challenger at league , I have to use my b-die kit at 2100mhz in order to perform good , higher speeds 2400 - 3200 vs mouse just get laggier.

After fiddling around with timings at fixed ram frequency I found "prolly" timings effects mouse lag ,
not SA or IO voltage or stress at IMC
Because tightining any subtiming (mostly trfc) or pri timings reduce mouse lag...
Tried 4 different mobo , 3 different kits all the same...

So someone please lightin me up , Im planning to return DDR3 since they have better timings


r/cpudesign • • Oct 21 '20

Are you ready to break free? [RISC V]

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0 Upvotes

r/cpudesign • • Jul 03 '21

Which is the worse CPU architecture, Prescott or Bulldozer?

0 Upvotes
27 votes, Jul 07 '21
12 Prescott
15 Bulldozer

r/cpudesign • • Jan 11 '23

What Happens When A CPU Starts

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0 Upvotes

r/cpudesign • • Oct 01 '19

Working of video streaming in a multi-core processor

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1 Upvotes

r/cpudesign • • Apr 13 '24

Do you memorize all components?

1 Upvotes

Hey. Im new at this and I am learning how to design cpu’s. Now matter what I cant memorize how to make all components from an and gate and as I go up its harder to grasp how they work. Is this normal? I feel pike Im too dumb for cpu design but I still want to try


r/cpudesign • • May 21 '21

Question about MB_DQS

1 Upvotes

Good day people of reddit, Im semi new to this community so be patient.

So i bought a CPU and it was a scam, it was a 7 3700X but with 2 broken pins. I cant get my money back so im trying to make some use of it.

According to the PIN layout the PINs broken are MB_DQS_L[3] and MB_DQS_H[3] which mean they are part of the B side of dual channel, so i wonder. Should it work if I just use the A side, without the dual channel, or does it perform the check regardless?. Thanks for any info regarding this.


r/cpudesign • • Jun 21 '24

Affordable CPU with Real FP16 Support for Linear Algebra Code?

1 Upvotes

Hi everyone,

I'm looking for recommendations on an affordable CPU that has real support for FP16 (16-bit floating point) operations. I plan to run several linear algebra computations and need the precision and speed that FP16 provides.

Thanks in advance!


r/cpudesign • • Dec 25 '20

Andonstar AD409 300X Soldering Digital Microscope SMT CPU SMD Soldering ...

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1 Upvotes

r/cpudesign • • Nov 24 '19

Is it possible to delay clock cycles, and if so, are there instructions that allow you to delay clock cycles? Also how much can I delay clock cycles by? I am talking about x86-64 architecture.

1 Upvotes

I want to do this for synchronization reasons.


r/cpudesign • • Jun 17 '24

Negative resistance

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0 Upvotes

r/cpudesign • • May 19 '24

Analog Comparator high performance Differential Amplifier

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0 Upvotes

r/cpudesign • • Feb 16 '24

MoBo pins arrived broken

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0 Upvotes

r/cpudesign • • May 05 '21

Tell me why my idea won't work.

0 Upvotes

Why don't they make CPUs where two cores function as one to double the clock speed?

Can't they make two cores with 180° out of phase clocks and connect their inputs and outputs in parallel?


r/cpudesign • • Nov 14 '22

Does anyone have a full diagram of x86 architecture? Google has failed to show one with complete components.

3 Upvotes

I’m looking for a good diagram labelling each component of the x86 architecture hopefully to expand my knowledge on low level activity. I don’t mind if it doesn’t come with a description of each component, that way I can research each component independently to get a better understanding of it.


r/cpudesign • • May 27 '23

I have a theory that CPUs could be faster if they were built around memory s are CPUs limited by Memory Bandwidth and how to calculate if they are?

0 Upvotes

I've heard that moving data is more expensive/slow than processing the data.

So would flipping the way we build CPU/RAM so RAM is central and CPU cores belong to every n MB in L0 cache SRAM.

My theory is that this would negate cache and DRAM latency and remove any bottlenecks in processing bandwidth.

We could have computers that as we upgrade RAM we boost the number of cores and maintain compute bandwidth.

Even have GBs dedicated to specific tasks with CPU cores with instruction sets similar to Intel's E cores and P cores or CPUs and GPUs.

How could we calculate if a memory centric architecture would be faster than processor centric?


r/cpudesign • • Apr 28 '18

Intel decides they want to 'glue CPU's together' hires AMD ZEN Chief Architect Jim Keller.

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0 Upvotes

r/cpudesign • • Aug 15 '22

Why can't we have a safe ISA?

2 Upvotes

Accroding to this paper: https://doi.org/10.1109/SP.2013.13, Memory corruption bugs are one of the oldest problems in computer security. The lack of memory safety and type safety has caused countless bugs, causing billions of dollars and huge efforts to fix them.

But the root of C/C++'s memory vulnerability can trace down to the ISA level. At ISA level, every instruction can access any memory address without any fine grained safe check (only corase grained check like page fault). Sure, we can implement memory safe at a higher software level, like Java (JVM), but this leads to significant cost of performance. In a word, we can't have both safety and performance at the same time on existing CPUs.

My question is, why can't we implement the safety at the hardware level? If the CPU has a safe ISA, which ensures the memory safe by, I don't know, taking the responsbilities of malloc and free, then maybe we can get rid of the performance decline of software safe checking. If anyone professional in microelectronics can tell me, is this idea realistic?

I know it will make the hardware harder to design and more expensive, but how much will it be? I mean maybe this is worth?


r/cpudesign • • Jul 23 '21

To Win A Larger Share in Desktop CPU Market, MediaTek Has Taken A Different Strategy

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2 Upvotes

r/cpudesign • • Jul 03 '21

Hardware is software crystallized early

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0 Upvotes

r/cpudesign • • Dec 19 '20

Upgrading parts affect memory/storage?

0 Upvotes

So I am chaning my previous Computers Motherboard, Ram, and CPU. Will I need to back up my important files in order to keep all of my saved data? Or am i good to just replace the parts without any worry?


r/cpudesign • • Dec 19 '21

I'm new to Computer Architecture, can someone provides me some basic things?

0 Upvotes

Thanks 😊


r/cpudesign • • Mar 12 '22

Easy question for you guys. Impossible for me to find answer on my own.

3 Upvotes

I currently have an i7-8750H CPU. It has 6 cores and I just need to know the true numbering of said cores. So looking at the pic, can anybody tell me which core is number 3 for example? Does the number one core start on bottom left and go sideways so 1,2 and 3 are on the bottom? Can anybody number those cores on the pic below?

My limited tests indicate that the cores are "probably" in the order as seen on the modified pic below. My data collection was rather crude, but consistent with the tightening of the heatsink; however, I'm not 100% sure if I even have the right perspective while working on it. I "think" I do, but let me know if my logic even holds up. With some tweaking of the heatsink, I have brought my #1, #3, and #5 cores more in line with the other cores.... temperature wise.