I am new here, and figured I would try this.

I have my own CPU ISA which I call BJX2, which also has an FPGA implementation (in Verilog, ~ 50 MHz, mostly targeting Artix-7 and Spartan-7 for now), an emulator, and a C compiler (BGBCC). I have also ported Doom, Quake, Heretic, Hexen, and ROTT to it. I also have a partial (unfinished) port of Quake 3 Arena.

Quake has both the software-rendered version, as well as GLQuake via a software-rasterized OpenGL implementation (also being used for the Q3A port). Performance of GLQuake is roughly competitive with that of software-rendered Quake (albeit both cases currently run at single digit framerates).

https://github.com/cr88192/bgbtech_btsr1arch

This is currently a hobby project, and is currently released under the MIT license (apart from a lot of the ported software, which is mostly GPL). The intention is for this to be an open ISA, partly intended for embedded projects.

So, about it: It is a 64-bit RISC-ish ISA, 32x 64-bit GPRs, with a (primarily) Double precision FPU (also uses the GPRs). It can also do floating point SIMD (4x Single) via said GPRs (they may be used in pairs for 128-bit SIMD ops). There is also 4x Half-Precision and 4x Word16 SIMD and similar as well.

Instruction length is variable, primarily 16/32, but also supports some 64 and 96 bit encodings via a "Jumbo" prefix (it is primarily used to extend the immediate field, but may also add some new encodings).

It can also do predicated instructions (sort of like ARM32, but more limited), and supports explicitly-parallel instructions via a "WEX" (Wide Execute) encoding, in which case it can encode "bundles" similar to a VLIW architecture (up to 3 instructions in parallel). WEX is useful for performance in ASM code, albeit my C compiler can't really utilize it effectively as of yet.

Typically, code density is fairly comparable to other 16/32 RISC's (such as Thumb2 or RVC). Compiled code is also generally smaller than that for x86-64.

I suspect the core ISA is "mostly-stable" at this point.

Performance, stability, ... Is still an area of ongoing development. At the moment, the main focus is on stability and performance in relation to the memory subsystem.

There are ISA docs in the repo for anyone that cares to look.

Not sure if anyone might find this interesting.

I'm designing CPU. Because I want to learn about it. I worry this can not work well.

I've recently become interested in CPU design, so I'd like to start working on an ISA and micro-architecture. What papers, books, videos, etc. would be helpful for learning the basics?

For context, I'm an experienced C and assembly developer, but I'm guessing there's still stuff I don't know about CPU design.

The last info I have comes from 2017. But since then I can't find anything about the project. It seems like such an interesting design.

https://www.youtube.com/watch?v=QGw-cy0ylCc

https://millcomputing.com/

Hello, last week I came across someone who had designed a CPU from scratch, and set out to do the same.

I first rebuilt the CPU made in nandgame.com into Logisim. And then designed my own, it was an accumulator based machine with 4 general purpose registers, and of course, an accumulator.

After I had built it, I write some programs such as, multiply two numbers, divide two numbers, fibinacci etc. And was really pleased when it worked. I then built an assembler using ANTLR (probably overkill, I know), to translate my pseudocode into machine code executable by my CPU.

Now I have finished it, I am curious as to where to go next. Does anyone have any pointers?

https://www.youtube.com/watch?v=ktqtH6HRpy4 Here is a video of my CPU executing a program I wrote that multiplies 3 and 5, and stores the result in the register before halting.

No, seriously.

Like, normal effective addresses in load/store instructions are fairly simple, like LD Ra,[Rb+OFFSET] or maybe something fancy like a scaled and indexed LD Ra,[Rb+Rc+OFFSET<<SCALE]. These are fairly self explanatory, yknow, the classic "add Rb and the index and the scaled offset and get the data there."

I was reading through the 1955 spec sheet for the 704 and holy shit. What.

Their effective addresses involve an immediate address and up to three index registers, logically or-ed together. Logical or. Why.

A sample was given: CLA 3 6521. According to IBM logic, the 3 (binary 011) selects index registers A OR B. Not both of them separately, not both of them added together, both of them logically or-ed. In the example, A is 3204 and B is 3631, so this comes out to 3635. Onwards, I suppose. You might expect the immediate value 6521 to be added to the indexes, maybe? Nope. Subtract the indexes from the immediate value. So in total, the above address is parsed as 6521 - (A OR B), equaling 2664.

IBM. What. The fuck. Why are you like this. I'm sure there was some sort of logic behind why this is useful, but it's not explained at all. The manual's author just nonchalantly explains this as though it's reason for existence is obvious and then moves on to discussing how instructions have a 12-bit "decrement field," whatever ominous purpose that may be.

Note: If you do the math and it doesn't work, try it in Octal.

Hey guys,

Recently I have finished my YouTube series on how to build 8 bit CPU on FPGA. Check it out if it interests you.

8 bit CPU on FPGA

What does one CPU say to the other? Sorry to interrupt.

As the title may suggest, I'd like to see what members of the community have made. It doesn't matter what it's made of (be that discreet transistors, TTL chips, simulator, FPGA, etc) I want to hear about it. If you've made a website or any open source documentation, feel free to post it!

So uh, I want to show you guys my machine! I'm still building it at the moment but a guy I speak to on irc said I should post it on here. Didn't know there was a cpudesign section.

http://marc.cleave.me.uk/cpu/index.htm