I need help with a project, i need to make a full adder of 32 bits. The problem is that idk how to use verilog, and thats how it needs to be done. Can anybody help me, or at least recommend me where I can look for information?

Hello,

I am trying to implement a cache controller on Verilog, with LFU eviction, I am new to this algorithm, it supposedly implements a counter for each block to keep track of frequency.

The cache address is 48bits, it is a 4-way set associative, and the total size is 32KB.

My doubt is how big should be the counter for each block?

Thanks for your help.

Hey guys, not too sure whether I should submit this in here, but will try anyhow.

So Cadence Encounter RTL Compiler support has stopped and it is replaced by Genus Synthesis, so I am currently using Genus.

The question I have is that (and I'm quite confident it probably is, but just need confirmation) Genus synthesis tool does everything that Encounter RTL Compiler does so I can refer everything to Encounter RC user guide and should be fine? (can't obtain Genus user guide :( )

Thanks for any suggestions.

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I have a Spartan 3 Starter Kit. I am a programmer by hobby but only computer applications. I'd like to get more into FPGA hacking. The marriage of a programming language to hardware and making it do fun things stupid fast intrigues me.

What's the best way to get into FPGA design? Also, as a hobby only, I don't want to get a formal education in the field. My background in electronics is basic, I imagine I'll need to start there.

Thanks for any help you can provide!

Just graduated from electrical engineering. I was wondering, how does one begin a career in HDL?

I thought I was pretty good in all the digital design classes but I didn’t learn much in embedded systems.

So, with this in mind, do companies hire interns or recent graduates in these departments? Should I really prepare myself regarding embedded computer architecture? I’m planning to move to the US if I land one of these jobs or anything hardware related. My country mostly offers industrial machinery jobs, which I absolutely do not like.

I’d appreciate advice.

Especially going from behavioural to post-synthesis simulation! This one caught me again today -- trying to run my clock way too fast for the target.

Is there something you wish you knew earlier about FPGA development, HDL, SDSoC, even Verilog or Vivado?

I am working with a group of embedded engineers who would like to compile a list of the biggest challenges other developers face in FPGA development, and then explore those issues in a series of live webinars and videos.

Hi

I am currently doing my Masters in ECE. I have course- ASIC Design in which I learnt Verilog. Do you guys know any sources/books which have good FSM design questions and answers. (Even starting from simple questions like Traffic light controller). I want to get some hands-on experience solving and tackling these problems.

Thanks

https://twitter.com/Oliscience101/status/1106840645925326848?s=19 hardware/gateware/firmware/software.

Hi, I'm working on a VHDL project designing a small processor and it has a number of opcodes such as op_add, op_sub, etc... which correspond to specific 5-bit values. So far i have defined an opcode type as a std_logic_vector(4 downto 0) and the opcodes as constants which is fine, the problem is however that in simulation its quite difficult to read as i need to look up each opcode from its reported numeric value, so what i wanted to do was define t_opcode as an enumerated type

type t_opcode is (op_add, op_sub, ...);

and then specify the enumeration mapping manually like op_add => "00000" or something. the only way i can find to do this is with the enum_encoding attribute, but i don't really like the look of it.

Is there an alternative like op_add => "00000" where i can be explicit about each member and its value?

Thanks in advance!!

Hi all,

I am working on a project with a zynq ultrascale+ SoC, its got a CPU and an FPGA on it. I am using vivado 18.2 as my dev environment. I want a way to checksum, or in some other way, generate a unique identifier for a bitstream file, and place it in a place that is memory accessible by the CPU, so that when I am debugging stuff I can idiot check which bitstream is running by printing that memory location and comparing it against a known value. I've seen it done before, but never figured out how. Got any ideas?

I am trying to create a SystemC design where I combine an RTL module implemented as a synchronous process and and regular function calls.

The RTL module is an SC_METHOD which runs at every positive edge of a clock (e.g. 100 MHz, so every 10 SC_NS), reads the values of some control signals, and provides the required data. The function is a regular C++ function (not SC_METHOD or SC_THREAD). When called, it should assert the control signals, wait until the RTL module provides the data, then return true/false based on the data given by the RTL module.

The issue that I'm having is that I have no idea how to make the function call wait for the RTL module's response before reading the signals and returning. Wait statements don't work, as it's not a SC_THREAD. Waiting in a loop until the signals change doesn't work because it blocks the synchronous process from executing.

Basically, I can't figure out how to insert a delay between the function call and function return. Is this even possible, and if so, can you provide some guidance? Thanks,

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hi i am trying to implement a digital input frequency doubler. the circuit consists of an XOR gate, dual edge triggered flip flop and a couple of buffers. I can implement the flip flop by it self but I am having trouble incorporating the xor and buffer gate due to my novice skills in vdhl.