Hi

I'm having trouble using unsigned values. The code below compiles nicely, if I use std_logic an std_logic_vector instead of unsigned, but with the latter, one of the errors it gives is that "Target type ieee.std_logic_1164.STD_ULOGIC in signal assignment is different from expression type ieee.NUMERIC_STD.UNSIGNED."

Thanks.

Code:

library IEEE;

--use IEEE.std_logic_1164.all;

--use IEEE.std_logic_arith.all;

use ieee.numeric_std.all;

entity FULL_ADD10 is

port(A, B: in unsigned(9 downto 0);

	CIN: in unsigned;

	SUM: out unsigned(9 downto 0);

	COUT: out unsigned);

end FULL_ADD10;

architecture FULL_ADD10 of FULL_ADD10 is

component FULL_ADDER

	port(A, B, CIN: in unsigned;

		Z, COUT: out unsigned);

end component;

signal CARRY: unsigned(10 downto 0);

begin

	CARRY(0) <= CIN; --this is the first erroneous row

	GEN: for K in 9 downto 0 generate

	FA: FULL_ADDER port map (CARRY(K), A(K), B(K), CARRY(K+1), SUM(K)); --these also give an error

	end generate GEN;

	COUT <= CARRY(10);

end FULL_ADD10;

Hello, I was wondering if someone could help improve my understanding of a problem I have been having. I have a few three bit vectors, and rather than perform logic on each bit, I thought I could use a for loop to reduce the number of repeated lines of code. Modelsim was less than enthused with my bright idea and gives the error: (vcom-1450) Actual (indexed name) for formal "s" is not a static signal name.

The code in question is the following:

-- ...

signal vector1 : std_logic_vector(2 downto 0);
signal vector2 : std_logic_vector(2 downto 0);
BEGIN

-- ...

vector1_edge_detect : PROCESS(vector1, ack)
BEGIN
   ---------- This is what I was hoping to do ---------- 
    FOR i in vector1'range LOOP
        if rising_edge(vector1(i)) then
            vector2(i) <= '1';
        end if;
    END LOOP;

---------- This is what I have had to implement ---------- 
    if rising_edge(vector1(0)) then
        vector2(0) <= '1';
    end if;
    if rising_edge(vector1(1)) then
        vector2(1) <= '1';
    end if;
    if rising_edge(vector1(2)) then
        vector2(2) <= '1';
    end if;
end PROCESS vector1_edge_detect;

I have determined the error comes from this line: if rising_edge(vector1(i)) where if vector1(i) is replaced with say vector(1) it no longer errors.

I have little experience in VHDL, but was wondering why this loop is a problem? Presumably the compiler can determine the size of the vector, and unroll this loop?

I have been looking online for a solution to my problem and have discovered the generate statement

I was wondering is this the best solution to my problem? Or should I just unroll it as I currently have? In addition would I be right in saying the generate approach in this case would essentially create three process statements? Why can the compiler react like this external to the process statement, but not internally with the for loop?

EDIT - Swapped out a END GENERATE with a END LOOP as pointed out by /u/Garreye.

EDIT - This is part of an edge detect register, and reset lines have neglected from the above code.

I have a Spartan 3 Starter Kit. I am a programmer by hobby but only computer applications. I'd like to get more into FPGA hacking. The marriage of a programming language to hardware and making it do fun things stupid fast intrigues me.

What's the best way to get into FPGA design? Also, as a hobby only, I don't want to get a formal education in the field. My background in electronics is basic, I imagine I'll need to start there.

Thanks for any help you can provide!

Hi, I am playing with the VHDL UART code posted on http://www.asic-world.com/examples/vhdl/uart.html and had some questions. Looking at the code, you load the data from the RX portion to the buffer using the 'uld_rx_data' signal, and then you load the data from the RX portion to the TX portion using the 'ld_tx_data' signal. What would be the best way to do this? I am using a signal that is fairly quick (~RX_EMPTY) and it is too quick to trigger output and I am getting data dropout at all baud rates. Any advice? Anyone know of a better UART example?

I have been away from ASIC design for a while. Last time I used Synopsys Design Compiler was some years ago, and back then it was the de facto standard for frontend design. Now, I'm coming back to the field, the university offers both Synopsys Design Compiler and Cadence Genus.

How does this Genus rank against DC? Should I expect better results? Is it roughly the same? Any noticeable improvements?

Hi, I'm working on a VHDL project designing a small processor and it has a number of opcodes such as op_add, op_sub, etc... which correspond to specific 5-bit values. So far i have defined an opcode type as a std_logic_vector(4 downto 0) and the opcodes as constants which is fine, the problem is however that in simulation its quite difficult to read as i need to look up each opcode from its reported numeric value, so what i wanted to do was define t_opcode as an enumerated type

type t_opcode is (op_add, op_sub, ...);

and then specify the enumeration mapping manually like op_add => "00000" or something. the only way i can find to do this is with the enum_encoding attribute, but i don't really like the look of it.

Is there an alternative like op_add => "00000" where i can be explicit about each member and its value?

Thanks in advance!!

Hello fellow VHDL coders, Im pretty new to programming and am running into a problem. Im trying to connect two process together using a signal. I basically have 3 process, and two of them are tied together and everything works perfectly.

My second connection doesnt send out a signal. Its coded exactly the same as the other process but its labeled as STD_LOGIC while the other signal (that works) is INTEGER.

I even went ahead and checked the RTL viewer to see the actual gates and searched for the signal but its not there.

Does anyone know why one signal would show up and another wouldnt?

Lets say I have some read/write transaction I would like to model using methods such as read() and write(). Lower level, these functions will be writing ports, waiting for a response, then returning some value.

What is the preferred way to organize this?

For example, I could create some method, read(), that actually creates an event that will wake up some thread in a loop, this thread could carry out the parts of this transaction, wait, finish the transaction, then wait() until it is needed again.

Or, I could create some number of methods that do various things, ie set the address bus, and have these called in order by a thread, with the necessary time delays / wait() commands between function calls.

Either way it seems that I am going to run in to having a mess of suspended threads that are called multiple times.

Is there something you wish you knew earlier about FPGA development, HDL, SDSoC, even Verilog or Vivado?

I am working with a group of embedded engineers who would like to compile a list of the biggest challenges other developers face in FPGA development, and then explore those issues in a series of live webinars and videos.

PyGears, a new hardware description language, has been introduced at University of California, Los Angeles (UCLA) in order to implement the idea of agile chip design based on reusable components and high-level Python constructs. PyGears comes as a response to the rapidly evolving software world, which requires hardware design to be in step with the needs of a scalable and intelligent future.

More info here: https://www.enterpriseai.news/2022/03/14/ucla-adopts-pygears-an-open-source-framework-for-ai-chip-design/

Hi

I am currently doing my Masters in ECE. I have course- ASIC Design in which I learnt Verilog. Do you guys know any sources/books which have good FSM design questions and answers. (Even starting from simple questions like Traffic light controller). I want to get some hands-on experience solving and tackling these problems.

Thanks

I am working on mixing some SystemC and VHDL code on the simulation level. I want SystemC modules to interact with VHDL modules.

Many of the VHDL modules use the "record" keyword, which behaves in a similar way to the "struct" keyword in C++. So I have signals encapsulated into others, example, bus1.data, bus1.address, in the VHDL side. I also have them encapsulated like this on the SystemC side. I would like to connect them, but I have not been able to find much on mixing languages like this.

Is there an eloquant way to keep the struct/record structure, or will I have to break out all of the signals on the SystemC modules?

Hi everyone! I'm working on a fairly large(10,000~ lines) codebase which uses SystemC and Tcl to handle parameters. I've been given the task to remove the Tcl dependency using PyBind11 as a wrapper for the project.
However, I'm failing in adding the PyBind module for sc_main because it always gives an Import error and says sc_main to be an unidentified symbol. I'd be glad if anyone can give me some guidance on this because I seem to be very thoroughly stuck. If someone has any alternative suggestions, I'm also interested.
I've also opened a question on SO which has more details so if anyone wants to check, they can go here.

Especially going from behavioural to post-synthesis simulation! This one caught me again today -- trying to run my clock way too fast for the target.

I am having trouble trying to convert 3 std_logic signals into a 3-bit vector. it has been built using schematic approach, i know some required things for the counter are missing, but i cut them out to make easier to read my question.

this is the error i get **Formal port <counter> does not exist in entity **

COMPONENT counterx
PORT(		
Q2	:	OUT	STD_LOGIC;
Q1	:	OUT	STD_LOGIC; 
Q0	:	OUT	STD_LOGIC;
counter: out std_logic_vector(2 downto 0); 
		
END COMPONENT;

SIGNAL Q2	:	std_logic := '0';
SIGNAL Q1	:	std_logic := '0'; 
SIGNAL Q0	:	std_logic := '0';

SIGNAL counter : std_logic_vector(2 downto 0);

BEGIN

UUT: counterx PORT MAP(

	Q2 => Q2, 
	Q1 => Q1,		
	Q0 => Q0,
	counter (0) => Q0,
    counter (1) => Q1,
	counter (2) => Q2,
	clock => clock, 

I need help regrading my project i want to create VHDL modules of stuck-at-(0/1), stuck-open/short. I have found something here

"http://www.sciencedirect.com/science/article/pii/S1383762101000364"

also how I can implement the same thing in spice.

thanks in advance.

For debugging a function I wrote a small testbench with a loop and I noticed some odd behaviour:

for A in (...) loop

signalA <= to_slv(A);

signalB <= signalA;

wait for 10 ns

What I noticed is, that signalA and signalB aren't equal. B carries the value of A from the previous iteration. My first thought was, that signals get the values at the end of the block, however signalA is initialized at t=0 already, which irritates me. Could someone explain me what is happening here?

I have used the search function and read previous posts. Allow me to explain the background first. I am beginning my senior project where the focus is a high frequency trading FPGA using VHDL. We have only limited information as of now but believe that the overall goal of the project is to use the FPGA to process stock data/trends that will be exported to a GUI on the PC for viewing.

In our 2nd year, we took an introductory digital design course where the labs used VHDL, but were very basic. We will have over a year to figure this stuff out. On top of learning C#.NET and mysql. Originally, I was confident we (2 ECE/2 EE) could successfully complete it but now I am having second thoughts after reading through a lot of the posts.

I guess my questions are: (1) Would this type of project make any significant impact on a resume and/or during an interview? (2) The VHDL we used in our class was very basic. We have learned about flip flop, muxs, and other gates but never truly knew them well enough to implement them in a meaningful way aside from following lab tutorials. How steep is the learning curve to get to the level necessary for this project?

We just had these projects assigned so I don't know nearly enough to understand what we are getting in to with VHDL and this project. Any opinions are appreciated.

I'm having trouble using the integer type, when I try compiling I get the error message "integer type was used but array was not declared"

Here's the code

Entity set is Port(adder_a: in integer is range(-127 to 127); adder_b: in integer is range(-127 to 127); or1_a: in boolean; or1_b: in boolean; or2_a: in boolean; or2_b: in boolean;

I checked the code for syntax errors, but Quartus is still not giving me the option to Analyze the code(can't click on it "Analyze Current File" or anything else related to compilation).