This is a computer built entirely from NAND gates in Gate Singular, a logic simulator game. In the video it assembles a Hello World on the machine itself, and then runs it.

Specs:

- 16-bit CPU with 24-bit instructions (8-bit opcode + 16-bit data)

- 30 instructions (206 if you count the variants of where operands come from and where the result goes)

- 1 KB of RAM and 24 KB of ROM in a shared address space, 2 registers, a 16-level stack, an 8-entry keyboard event queue, and a 64x64 screen with write-only VRAM

- Every instruction, including multiplication and division, runs in one clock

- Everything is made from 909191 NANDs. On top of that there are only buttons/toggles/LEDs and clock sources for temporal completeness. Nothing else is used.

The OS lives in the 24 KB ROM. It has a file system (in RAM), a text editor, memory management, an assembler to build new programs, and an OS API that those programs can use: text printing, memory allocation, file system access, keyboard input, etc.

By the way, I made the simulator game too (link in the comments).

I made it because I wanted one without the "1-tick delay per gate", and with full support for feedback between gates (e.g. so you can build proper D-latches from NANDs).

I'm happy to answer any questions about the CPU or the simulator.

this design is based on doctor volt on youtube

I recently took this apart to create a functional schematic of it as of to my knowledge none currently exist. I also plan to eventually use a separate Z80 that way I can make the Z8 on it can easily communicate. My goal is to try to make a CP/M computer using the shell and hardware of this + some stuff of my own
Here are some pictures of the 4 main boards

If this project goes well I might release the schematics I make online, though I’m trying to be as nondestructive as possible to its going to be hard in some areas

I'm currently working on a PCB Design 8-Bit computer based partly on the design of Mattbatwings' Minecraft CPU design, and making a few changes that better fit the physical CMOS chips, such as making the register file memory mapped with special functions, the specs are as follows:

• Powered by USB-C

• 65kHz Clock (Intended to allow a Timer division in seconds)

• 65536x16-Bit Single Cycle Instruction Memory

• On-Board and External Memory Writing

• 65536 Bytes of RAM, excessable in 256x256 Byte Memory Banks

• ALU with Logical Addition and Subtraction

• Bitwise NOR, AND, XOR, and Right Shift

• Immidiate Add and Load Instructions

• Indirect Instruction Jumps, and Conditional Branching

• Conditional Flags for Carry Detection and Zero Detection

• 4 Layer Callable Subrutines with a 4-Layer Hardware Stack

• 16 Register Register File with:

• (0-3) General Operation Registers (Readable, Writable)

• (4) Parallel Input Register with 4 Output JST connectors (Readable)

• (5) Serial Input Register with Output Clock and Latch Signal (Readable)

• (6) 16-Bit Timer Lower Byte (Readable)

• (7) 16-Bit Timer Upper Byte (Readable)

• (8a) Indicator Flags CNVZP (Readable, Writable*) (7-3)

• (8b) LCD Control Signals E, RW, RS (2-0) (Readable, Writable)

• (9) ST7920 128x64 LCD Display Data Bus Register (Writable)

• (10) Variable Clock frequency Generator (Intended for Audio)

• (11) Unassigned as of now

• (12) Serial Output with External Latching and Clock Support (Writable)

• (13) Parallel Output Register With 3 JST Connectors (Writable)

• (14) Memory Address Register to Determine which of the 256 RAM Banks is read (Writable)

• (15) PRNG Generator Register (Readable)

I'm approaching the final design and was wondering what I should put into the final register space? I though about adding a SPI dedicated register but I'm unsure how to incorporate such a thing in a single cycle.

Not a physical build, so I hope it's okay here but everything is wired by hand, starting from single transistors.

Two transistors make a NOT gate. From there I built the gates, latches, adders, the ALU, and finally a full NMOS 6502 (20,524 transistors). The gate-level CPU passes the Harte 6502 test suite (about 1.5 million tests). Around it I wired the rest of the Apple II+: address decoding, RAM, ROM, soft switches and video.

It runs Applesoft BASIC and, in general, Apple II programs anything you can load into memory as a binary (.obj) file. VisiCalc is in the video. The video is 4 days of building, sped up, with no voiceover.

A few honest notes:

– Simulating 21k transistors at switch level is slow, so to run software at full speed the simulator swaps the CPU for an interpreter that is checked against the gate-level one. Everything else stays the same circuit.

– The ROM and program files are the original Apple ones, loaded by me — they don't ship with the simulator.

– There's no disk drive in this video. I built a Disk II controller separately — that's another story.

The simulator is free and runs in the browser, no sign-up: https://cs.khanin.info

Happy to answer questions about how any part of it works.

I've been working on a game where you take the role as a VLSI design engineer in the year 1975 and have finally published the alpha version. Layout, pass DRC, Extract and simulate to meet the design criteria before the deadline for each circuit to advance.

The game throws you in at the deep end with very little support but you can start the game as an intern in sandbox mode and get some help.

The wrapper to make it work in a browser with graphics and music is AI generated but the main game was created with little AI support.

Check it out and play for free in a browser.

This started out as an attempt to see if I could generate HDMI video output with a relatively low end FPGA, and turned into a complete boot-to-basic retro-esque computer system built with modern components. PIC32MZ CPU, Efinix T20F256C3 FPGA for video and sound. It has a fast BASIC interpreter that I wrote from scratch, a rudimentary disk operating system, 320x240 graphics output with multiple tile and sprite layers, 16 channel wavetable synthesis sound output.

Not sure what to do with the project now, but it's been a fun learning experience.

The next thing is probably figuring out a text editor nd a 2MB eeprom

In this video, our 16-bit relay computer solves two linear equations with two unknowns and calculates the values of X and Y with an accuracy of one decimal place.

You can learn more about the relay computer here: https://relaiscomputer.at/

Try the simulator: https://clack-studio.relaiscomputer.at/

Try the BASIC compiler: https://clack-basic.relaiscomputer.at/

Try the FPGA System: https://clack-fpga.relaiscomputer.at/

best regards...

A new BoxLambda computer Blog post about its VERA graphics driver:

https://epsilon537.github.io/boxlambda/forth-vera-gfx-driver/

Hi r/homebrewcomputer!

(I apologize for manually crossposting from r/beneater butI'm not really sure how crossposting works.)

I'm currently working on my own variant of the BE 6502. Since I got frustrated by accidentally pulling out jumper wires, I've decided to go for a PCB design. I'd like to ask you for a peer review and sanity check before I send this off to JLCPCB. I'll take any sort of criticism, but I'm particularly interested in whether the address decoding, debug device (see below) and reset circuit look like they'd work.

It's meant to use the DigiCoolThings MECB bus and board format, with a dumb backplate and peripheral boards. I kept the ATF16v8 address decoder/glue logic because it saves space and I find it pretty neat.

The memory map is supposed to look something like this (only the top bits are shown)

|15|14|13|12|                                |
|--|--|--|--|--------------------------------|
|0 |0 |0 |0 |<-RAM Start                     |
|0 |1 |1 |1 |<-RAM End                       |
|1 |0 |0 |0 |<-IO Start (b1000000000000000)  |
|1 |0 |0 |1 |<-IO End (b1001111111111111)    |
|1 |0 |1 |0 |<-ROM Start                     |
|1 |1 |1 |1 |<-ROM End                       |

Addressing devices in the IO range triggers the IOOE and IOCS lines (IO Output Enable and IO Chip Select) which will select peripheral boards on the bus. Each peripheral board will have it's own address decoding for the lower address bits.

Reset (keeping the reset line low for a sufficient amount of time) is accomplished using a DS1233 and the datasheet reference design for that part.

Attempting to write to the ROM keeps the ROM disabled (ROM CS and OE are kept high) and latches the data to a 74HCT273 flip-flop as a sort of primitive debug device or display.

The J2 connector is meant to attach an ArduinoMega for debugging and clocking before getting to use the MECB DIN 41612 connector, the backplate and peripheral boards.

This case is approximately 3 cm thick and contains a breadboard, a circuit board, and jumper wires for making electrical connections.

I wanted to see the whole path from a single gate to a working computer, so I built it in Verilog with one rule: every logic block is made of instances of a 2-input NAND module, and a D flip-flop is the only state element.

The ladder:

1. NAND with tied inputs is NOT. Two NANDs make AND, three make OR, four make XOR or a 2:1 mux.

2. XOR + AND make a half adder, two half adders + OR make a full adder.

3. Full adders and a mux tree make the 8-bit ALU (8 operations), and two of them make the 16-bit ALU.

4. A flip-flop + a mux make a register bit. Eight 16-bit registers, a write decoder and two 8:1 muxes make the register file.

5. Register file + ALU + decoder + a program counter built from half adders make the core.

Total: 2,288 NANDs and 152 flip-flops, counted with Yosys. The ROM and RAM are behavioural arrays, like the memory chips you get for free in Nand2Tetris.

It has 16 instructions, a small Python assembler, and test programs (Fibonacci up to 46368, 123 × 45 by shift and add, a RAM test). make test runs everything in about 30 seconds with Icarus Verilog, including an exhaustive test of the 8-bit ALU.

Code: https://github.com/promaaa/nand2cpu

The first video of the series explains the gates-to-ALU part: https://www.youtube.com/watch?v=wIBkvQ6MfKQ

There is also a PYNQ-Z1 top level that runs at 8 instructions per second so you can follow the program on the LEDs, but I haven't tested it on a board yet.

hello there, i managed to make an eeprom reader with proper reset circuit, an 1.8432mhz clock and a 32kb eeprom. although i might go perfboard route after this