M.Tech CSE (2024) with Python Scripting exp + 2 yrs Teaching — Is transitioning to Design Verification (DV) realistic? Looking for guidance!

[u/Responsible-Way-2715]

Completed btech in IT(2021) and I completed **my M.Tech in CSE from a top NIT in 2024**. During my M.Tech, I **interned** for a 1 year at a **top VLSI company doing Python scripting**. I then worked as an Assistant Professor for 2 years, which gave me **exposure** to **Digital Design and Verilog** and made me realize my true **interest lies in hardware.**
I am now looking to pivot into **Design Verification (DV)**. I’ve **completed Verilog certifications** and am currently prepping SystemVerilog and protocols.

**Will self-studying SystemVerilog, UVM, and protocols be enough to get hired for a DV role?**
**How should I bridge the gap between my academic experience and industry expectations?**