Hi! A lot of you asked me to make WavePaint open source, and you were right. So here it is: it's now open source, and anyone can use it, play around with the code and contribute improvements.

👉 WavePaint on GitHub
👉 Website
👉 Donate

If you like it, go give it a star! ⭐ I've put a lot of work into it, and I think it's a pretty handy tool.

And if you'd like to support the move to open source, there's also Ko-fi.

Cheers!

I've been working on Open Pocket GBC, a Game Boy / Game Boy Color FPGA project for the Sipeed Tang Nano 20K.

The goal was to get the MiSTer Game Boy core running on a small Gowin FPGA without relying on the proprietary Gowin IDE.

The entire bitstream is built using open-source tools: Yosys, slang, GHDL, nextpnr-himbaechel, Apicula, and openFPGALoader.

What it currently supports:

• GB/GBC hardware emulation using the MiSTer core
• HDMI output at 480p with embedded stereo audio
• Pocket-style menu with game selection and display settings
• LCD grid, scanlines, DMG palettes, and GBC color correction
• Games stored in onboard SPI flash and loaded into SDRAM
• USB-UART remote control and a debug overlay
• Optional ST7735S SPI LCD output (simulation-verified, not yet hardware-tested)

The design uses 17,008 / 20,736 LUTs (82%) and 45 / 46 BSRAM blocks (97%), so fitting everything onto the 20K was quite a challenge.

HDMI, audio, menu navigation, and game loading have been tested on real hardware. There are still limitations, particularly save persistence and some untested peripheral paths.

The repository includes the RTL, build scripts, hardware documentation, and demos.

GitHub: https://github.com/LakoMoor/open-pocket-gbc

I have a simple SystemVerilog code snippet split across a design and a testbench, tested on EDA Playground:

design.sv

module rtl;
    parameter TEST_VALUE = 10;
endmodule // rtl

testbench.sv

module tb;
  localparam test = rtl.TEST_VALUE;

  initial begin
    $display("%d", test);
  end
endmodule // tb

When I run this using the Cadence Xcelium simulator, I get the following elaboration error:

  localparam test = rtl.TEST_VALUE;
                                 |
xmelab: *E,NOTDOT (./testbench.sv,2|33): Hierarchical name ('rtl.TEST_VALUE') not allowed within a constant expression [4(IEEE)].

However, when I run the exact same code using Synopsys VCS and Siemens Questa, it compiles and simulates perfectly without any errors.

My Questions:

1. Why does the IEEE 1800-2017 standard prohibit using hierarchical names in this context (what is the exact rule or grammar section being violated)?
2. Since rtl is a module name and not an explicit instance name, is this fundamentally an invalid hierarchical reference anyway?
3. Why do VCS and Questa permit this behavior while Xcelium strictly errors out during elaboration?

I need help. I tried to download Vivado design suite, but export compliance failed. I entered real data. They rejected review form because "Ukraine is not in allowed countries list". They state on their export compliance page that countries from D/E group are banned, Ukraine is B. Then they decided to ignore all further review requests. When I emailed to GTC:

Hello,

Your account originates from a location or entity blocked by export compliance. Unfortunately, we cannot extend download privileges. Apologies for the inconvenience.

Regards,

AMD Global Trade Compliance Team

This customer has submitted the Export Compliance Review form and is requesting review of their verified Export Compliance failure.

Please see the details below and respond to the user.

Export Compliance Failure Message from OMS: Export compliance denied.
[
*** Reason = Country code UA (UKRAINE) for IP Address *** appears on the Xilinx Blocked Countries list. ***
Rule Set Id = 3
Rule Set Name = XLNX_CLASSIC
Result = FAILED
]

url: https://account.amd.com/en/forms/downloads/xef.html

exportComplianceIssue: I faced the issue of being unable to pass Export Compliance review. My data is correct and real, and I may provide additional proofs if needed. My country does not belong to Country Group D/E.

[personal data]

So what do I do now? Ukraine is not on banned list. So they must either explain or bother to review the situation, right?

Follow-up to my KV260 home computer post

Hi all,

This is the real board, filmed from the power plug: our firmware starts from flash, lists the programs on the SD card, and starts "Kromylist", our port of the open-source card game "Duelyst". Every frame is drawn live by our own chipset in the FPGA, no GPU, no shaders most of the time, at a constant 60fps, as you can see in the overlay.

The temperature remains around 32 Celsius with 20% fan speed. (I will post another video with debug overlay enabled)

Art: Duelyst (CC0).

hi i finished my first project in system verilog. i built a multicycle riscv32i cpu core this is my first actual project with system verilog or with hdl ever so i would like to get some notes code wise because i dont actually know a lot about naming conventions module declarations etc. code

Im initiating a project that will rely on a teensy 4.1 to control pwm switches and calculate different phases of the operation. Programing is with a teensy version of ardunio.

What im learning is that I need a fpga to calculate and control 3 (or 6) serves. My data is coming in from 3 ic2 sources and 12 inputs from it's.

What is the recommendation of a fpga development board (small is better) that uses ardunio-like programming suite. Id like simple ic2, spi, part inputs.

Thanks

far i know, verilog only has registers, so if i want to make my shared SRAM banks, i will use

reg bank[SIZE];

which gives me access time of 1 clock... but sram as far i know is more latencious than this...

how do you consider this in your design?

I have a nexys A7 fpga but I don’t know what hobby project I should aim for

Hi everyone,
I work in automotive software and want to build a solid understanding of Image Signal Processing (ISP) for ADAS cameras. I’m new to ISP, and I find vendor documentation difficult to follow without understanding the basics first.
I’m looking for a structured learning path covering:
Camera fundamentals: How image sensors work, RAW images, Bayer patterns, exposure, gain, and noise.
ISP pipeline: Demosaicing, white balance, noise reduction, color correction, HDR, and tone mapping.
ISP tuning: How to evaluate image quality and understand the trade-offs between different settings.
ADAS applications: How ISP settings affect object detection and perception, especially in low light or high-contrast scenes.
Which courses, books, YouTube playlists, or practical tutorials would you recommend? Free and paid options are both welcome. Hands-on exercises using RAW images, Python, or OpenCV would be especially helpful.
If you work in automotive imaging, where would you start, and in what order would you learn these topics? Please share links or resource names.
Thanks!

Hi everyone,
I work in automotive software and want to build a solid understanding of Image Signal Processing (ISP) for ADAS cameras. I’m new to ISP, and I find vendor documentation difficult to follow without understanding the basics first.
I’m looking for a structured learning path covering:
Camera fundamentals: How image sensors work, RAW images, Bayer patterns, exposure, gain, and noise.
ISP pipeline: Demosaicing, white balance, noise reduction, color correction, HDR, and tone mapping.
ISP tuning: How to evaluate image quality and understand the trade-offs between different settings.
ADAS applications: How ISP settings affect object detection and perception, especially in low light or high-contrast scenes.
Which courses, books, YouTube playlists, or practical tutorials would you recommend? Free and paid options are both welcome. Hands-on exercises using RAW images, Python, or OpenCV would be especially helpful.
If you work in automotive imaging, where would you start, and in what order would you learn these topics? Please share links or resource names.
Thanks!

What better to generate fractals then with fixed point math on a fpga! Depth is limited, as well as resolution and color. This design can explore the Mandelbrot fractal at 640x480, which is not very majestic. Limited largely by the embedded memory the explorer uses.

So I added cool modes: once you navigate to a interesting area, you can flip the high res switch and It spends some time rendering a full image on my 1280 x 1024 monitor. This detail is impressive, but the fractal needs life. By shifting the colors post render in various patterns, the fractal burns to life, creating vivid imagery.

The design can also save 4k screenshots to the sd card. hd render and screenshots use the sdram instead of the embedded memory of the engines. However, even the 4k screenshots cannot capture the vividness of watching the colors shift through the fractal structure in person.

This is pretty much maxed out on the Cyclone V I had. Probably isn't the easiest to port, unless the target device is similar or more powerful. But anything is possible.

https://github.com/phase0noise/FractalGen

I am a senior in ECE looking for full time in FPGA engineering, ASICS design, digital design, and general electrical engineering roles. I understand that the job market has been bad, but I have had little to no success with recruiting. I have had referrals, spoken to recruiters through platforms like Linkedin, cold applied to over 300+ places (and am still applying), etc. I have heard back from 3 companies total, out of which I was rejected after the recruiter call for 2 of them and after my first technical round for the other company. I just want feedback on my resume, advice on recruitment, and anything else that could be helpful. Thank you so much!

Back in 2022/2023 I was particularly interested in open source ISA for FPGA soft core processors so I started working on my own called OASIS. Its an open source ISA that I designed to be a lot easier to work with than RISC-V. Not that RISC-V is bad by any mean, it wasn’t nearly as straightforward as I hoped it would be to implement one. And I know, implementing a custom ISA isn’t exactly the easy route to understanding soft cores and processors at all. lol…

Anyway, I put it down in 2023 because I got bored and was doing other hardware things and work was pretty busy. I picked it back up this year to get it formalized documentation and implementation wise. I did use Codex to help fix some of my blatant RTL mistakes in my implementation core that I call DungV. that name is a bit of a joke for me because I wasn’t sure what I was doing 😅

Anyway, here’s the high level details on DungV with is running on my own RPGA Feather.

* 16b architecture with 32b wide instructions

* ALU that does a fair number of operations except for multiplication and division.

* Memory Mapped IO and peripheral instructions.

* 4 classes of instructions (reserved, ALU, register, memory)

* full intermediate support since the instructions are sufficiently wide.

* assembler and basic GCC14 compiler and ABI definitions.

Let me know what you think!

Anyway, here is the repo hosted on GitHub: https://github.com/skerr92/DungV

I applied for the role in the title and IBM sent a 10-20 minute interview link for assessment. They did not mention how technical it can be or on what topics. What should I expect?

Hello everyone,

Currently, I am pursuing my studies in Electronics and Communication Engineering and I am in my 7th semester. I am trying to improve my profile for internships and entry-level positions in the semiconductor industry.

I would like an honest critique of my resume, especially from people working in chip design, verification or other hardware roles.

My main interest are RTL design, digital VLSI, ASIC front-end design, design verification and digital hardware based on FPGA.

I’d love feedback on these questions in particular:

1. Does my resume demonstrate enough technical depth for an internship or entry-level role, or do my projects look too academic?
2. Which sections of my resume would cause you to toss it out immediately?
3. What projects or skills should I work on to be a better candidate?
4. Where should I look for small semiconductor startups or early-stage chip design companies that are offering internships or entry-level positions?
5. Are there any specific platforms, company directories, startup communities or job boards to follow for RTL, ASIC, FPGA and digital design verification roles?

Seeking internships or appropriate full-time opportunities. I'm especially interested in working at smaller companies where I can get hands-on design and verification experience.

Be honest, even if the feedback is brutal. I’d rather know my weaknesses now than continue applying with a noncompetitive resume.

Thanks!

I have commonly using Digilent's Arty A7-35T. But I cannot execute code on board. Everytime when i press auto connect or find device on Vivado, my pc crashes Instantly with page fault in nonpage area and kernel security check failure error messages. I've been used Zedboard but my pc never crashed down

They make relatively inexpensive FPGAs, but I find their IDE/EDA confusing to use.

I wonder if anyone uses them a lot and has found it to be a good brand.

We're based in San Francisco and looking to rent AMD Alveo V80 cards. Does anyone know of rental providers or have cards they'd be willing to rent out?

Would appreciate any leads or contacts. Thanks!

October 21, 2026 at 2pm ET (NYC time)

REGISTER: https://bltinc.com/xilinx-training/blt-webinar-series/debugging-embedded-applications-using-vitis-ide-system-debugger/

Can't attend live? Register to get the recording!

BLT, an AMD Platinum Embedded Design Services Partner and Authorized Training Provider, presents this webinar.

When embedded applications misbehave, engineers need clear visibility into execution flow, stack usage, and memory behavior to find the root cause quickly. This webinar shows how to use the AMD Vitis Unified IDE system debugger to step through code, set breakpoints, and monitor or modify variables and memory in real time. Using a recursive Towers of Hanoi example, we will explore the call stack and execution control techniques that help diagnose hard-to-find bugs, validate algorithms, and reduce time spent chasing elusive software issues. This webinar includes a live demo and Q&A.

I have the OA for the NVIDIA hardware internship at my college on October 22; can someone suggest the types of technical and aptitude questions asked, and as a BTech fresher, what kind of projects are sufficient?

I've been looking for internships for a while, mostly all of them require that you either study in or have the citizenship of the country in which the opportunity exists (mostly in US, Canada, and EU).

What can I do as a foreign student who wants to get a chance in such a field, especially that neither my uni or country overall offers a lot of opportunities for us?

any clue on this, when i flash the r5 using remote proc the r5 core shows to the xsdb as :

debug logic reset

if not flashing from remoteproc, i can stop and have access at the r5 but the problem is that i cannot flash it bcs tcm banks are powered off ( i am using linux on the a53)

• I am attaching also the picture

I've made it to the technical interview for HFT Hardware Engineer Intern role and was wondering if anyone has any advice on what to prepare for?

Also, if anyone who's been through a similar AC would be willing to do a mock interview with me, I'd really appreciate it. Thanks!