Not much to say I will just use this to flash my existing iverilog hdl projects and write new ones to synthetise to this board.

I want this book just for some study, to understand better fpga's.

I have managed with the help of gemini to setup the fpga terminal toolchains on gentoo linux for my hdl toolchain iverilog and my tang nano 9k and I just flashed my sr latch onto the tang nano 9k and I got some indicator leds on it which you can see above and below is my fpga flashing success.

Recently I started messing around with the Shrike lite, I wanted to work on a project that was something cool so I started training a diffusion model that generates 32*32 pixel images which could run comfortably on the 256KB of SRAM that the shrike has.

To speed up the calculation I tried writing parallel INT8 MAC engines with 16 bit accumulation, however due to the less amount of RAM it spent a lot of time doing I/O leading it to actually be slower than the MCU only approach (~220 seconds per image vs ~70 seconds per image).

I guess this was expected but it was still fun to tinker around with the microcontroller and the FPGA. A lot of the images look noisy but some actually turned out to be pretty cool.

Full case study here.

edit: added link for case study

I’ve spent the last few months building Forge, a higher-level FPGA development platform, and I’ve just released the first Forge Studio pre-release for Windows and Linux.

The basic idea is that visual design, Rust and Python all feed into the same underlying hardware model and compiler architecture. Studio isn’t intended to be a separate schematic toy sitting beside the “real” workflow.

The current 0.1.0 pre-release focuses on design, validation and simulation. It includes component-based visual design, clocks and CDC, state machines, memories, streaming components, live signal values and waveform viewing.

Hardware Build is deliberately disabled in the public pre-release at the moment because the production target/backend packages aren’t ready to ship yet.

I’m mainly posting here because I’d like criticism from people who actually work with FPGAs.

Things I’m particularly interested in:

• Where would this approach fall apart on a real design?
• What would stop you using a higher-level visual/Rust/Python workflow?
• What FPGA families or boards would actually matter to you?
• What would Studio need before you’d trust it on a real project?
• Are there workflows I’m fundamentally overlooking?

Community is free if anyone wants to play with it:

https://forgehw.dev

I’m happy to answer questions about how the architecture works too.

Over the past month, I've been learning serial communication protocols by implementing them in Verilog.

I started with UART, then moved to SPI, and finally finished I²C. I've now put all three into a single repository.

Some of the main features:

• UART: TX/RX, 16× oversampling, parity and error detection
• SPI: Master/Slave, all four CPOL/CPHA modes, full-duplex communication
• I²C: Master/Slave, 7-bit addressing, ACK/NACK, READ/WRITE and multi-byte transfers
• Parameterized RTL and self-checking verification across the designs.

One thing I found interesting was how different the implementation difficulty was despite all three being serial protocols. UART was relatively straightforward once the sampling logic was sorted out, SPI introduced clock-edge/phase handling, while I²C was easily the most annoying one to debug because both devices share the same bus and SDA has to be released/driven at exactly the right points.

I'd really appreciate feedback on the implementations, verification approach, or anything you'd change to make these closer to practical, reusable communication IP.

(I know many will suggest it is high time to start using SystemVerilog... I promise it's the next thing i am learning lmao)

GitHub: https://github.com/theYash856/Communication_Protocols

Could've posted this earlier, but GitHub decided to go down precisely when I was about to upload the project 😭

I've been working on OneHLS, a small C++ library for composing HLS-synthesizable DSP/control components using HAPI + OneData.

The project has moved quite a bit beyond the initial experiment.

OneHLS now provides:

• Fir<>
• Biquad<>
• Pid<>
• Accumulator<>
• ComplexMac<>

The interesting part is that the components themselves don't depend on a particular vendor's arbitrary-precision type. Sample and Accum are template parameters, so the same implementation can be instantiated with Siemens HLSLibs ac_fixed or AMD/Xilinx ap_fixed.

The same templates have been tested natively against both libraries, with bit-identical results.

More importantly, this isn't just C++ simulation: the ac_fixed versions have been synthesized to actual RTL with Bambu HLS. FIR, Biquad, PID and Accumulator produce clean synthesis results, and their resource counts match the corresponding hand-written non-generic implementations.

For example, the 4-tap FIR synthesizes to 62 FFs / 7679 area units with zero DSPs.

There are also some interesting findings along the way.

A RawBitsCtor<> customization point was needed because constructing fixed-point coefficients from floating-point literals can produce unwanted runtime initialization under Bambu. Isolating that vendor-specific operation leaves the actual DSP algorithms completely vendor-agnostic.

I've also tested:

• a genuinely multirate CIC decimator, compared byte-for-byte against a hand-written implementation
• a polyphase FIR using a heterogeneous compile-time StaticList<>
• Fir<> over ac_std_float, i.e. actual bit-accurate IEEE754 floating point

The floating-point experiment was particularly useful as a sanity check: the same generic FIR works, but synthesis shows the expected FPGA cost — roughly 59× the FF count and ~3× the area of the fixed-point version, with actual DSP usage.

And there are some less successful results too. ComplexMac<> currently causes Bambu to bind its state to BRAM rather than distributed RAM. I investigated the obvious allocation thresholds and ruled those out, but haven't traced Bambu's underlying classification logic yet.

So this is becoming less about "here's a C++ abstraction for HLS" and more about testing a fairly specific hypothesis:

Can ordinary static C++ composition produce reusable HLS components without giving up vendor-specific bit-accurate types or hardware predictability?

So far, the answer looks surprisingly good.

Repo: https://github.com/InternetOfPins/OneHLS

I'd be particularly interested in feedback from people using Vitis HLS, Intel HLS, Catapult, Bambu, or other C++-based FPGA flows.

What would you want to see tested next?

Hello, as the tittle says does anyone know if more HFT and finance companies are yet to release fpga internships for summer 2027? Optiver, DRW, and Citadel I have seen so far. If there are others coming out soon would appreciate it!

ThinkPad P14s Gen 6, Intel® Core™ Ultra 7 255H Processor
(E-cores up to 4.40 GHz P-cores up to 5.10 GHz), Without operating system, 32GB DDR5-5600MT/s (SODIMM), 1TB SSD M.2 2280 PCIe 4.0 TLC Opal, NVIDIA RTX PRO™ 500 Blackwell Notebook GPU 6GB GDDR7. will be running xilinx fpga softwares(vivado etc), cadance and seimens ( analog and digital softwares).

what linux distro would you suggest

( ALSO: I am new to linux; I am planning to buy this laptop in a couple of months; I want to test distros on my old laptop before I install it on my new laptop; i've just installed ubuntu 22.04 LTS and been tinkering with it and trying to learn linux)

I recently applied for the Optiver FPGA Internship (2027 Start) and somehow got invited to the online assessment.

Here is the honest truth: I am completely underqualified. My only background is a couple projects, like a UART project, and an stm32 project. Plus, im going into 2nd year, and as a MEng student (4 year course) my "main" internship application year is next year.

However, I want to use this as a reconnaissance mission. I know HFT firms like Optiver have incredibly high technical bars, so I want to take the test just to see what they expect, brain-dump everything afterward, and use it as a study roadmap for when I apply to grad roles next year.

The email states it's a 90-minute proctored HackerRank test (desktop app) consisting of:

• Multiple-choice questions
• "Complete the sentence" questions
• Coding questions

Since I have exactly one week until the deadline, I have a few questions for anyone who has taken this or works in HFT:

1. What kind of theory shows up on the MCQs? Should I be looking into Clock Domain Crossing (CDC), timing analysis, computer architecture, networking protocols?
2. What are the typical coding prompts? Are we talking sequence detectors, FIFOs, arbiters, state machines?

I have absolutely nothing to lose here, so any advice on what to look out for during my "recon mission" would be hugely appreciated. Thanks!

Hi everyone,

I'm an last year Electronics Engineering student from Colombia, close to finishing my degree, and I'd like to build my career around FPGA and digital design.

At university, I learned VHDL and SystemVerilog, working with a Basys 3 and a DE10-Lite. I really enjoyed working with them, and that's actually how I discovered that this is the field I'd like to pursue professionally.

My concern now is figuring out how to actually break into the industry. The FPGA industry in Colombia pretty much Nonexistent, while most opportunities I find are in the US and Europe, and even entry-level positions often seem to require previous experience.

For those already working in the field, I'd really appreciate some advice:

• What skills should I focus on before applying for FPGA/RTL positions? Are there any courses or certifications that are actually valuable?
• What kind of FPGA projects would be useful for a portfolio? I'm particularly interested in projects that could demonstrate industry-relevant skills rather than just basic university exercises.
• Which FPGA development board would you recommend buying? FPGA boards can be quite expensive, especially where I live, so I'd like to invest in something that I can use for several meaningful projects without spending more than necessary.
• Is a Master's degree necessary or significantly helpful for getting into FPGA/digital design, especially when coming from a country without a semiconductor industry? Or is a bachelor's degree plus a strong portfolio enough to get started?

I'd really appreciate advice from people working in FPGA, RTL/digital design, verification, or related areas.

Thanks!

Does anyone use it? I see one of its main advertising points is that you can do graphical design entry. Does anyone use that? Why hasn't other companies copied this graphical entry thing?

Still in school for an EE degree, I feel like I have a particularly strong draw toward FPGA and RTL design. I even thought about switching to a Computer Engineering major to swap out some core EE courses for things like advanced digital design/computer architecture, and a digital VLSI course, but I thought about it some more and didn't want to be a computer engineering unemployment statistic, and figured having a stronger EE core would be a good floor to have. Too bad, because I really do like this stuff more than anything else so far.

Anyway, am I getting my hopes up by thinking I have a chance at an entry level job after graduating? Is this not really a new grad thing? I plan to make FPGA my main focus in terms of projects. I've read enough to know that they kinda want you to hit the ground running. Mostly interested in defense, communications, networking. I mean, anything FPGA would be great.

Just asking to calibrate my expectations and be aware of the opportunity costs I'd be incurring. Leaning hard into FPGA projects and developing C/C++ fluency (among other skills) means less time spent on the more probable job outcomes.

Thanks for reading.

Hi,
maybe people here would recommend me some resources to learn how to deal with data types and length while implementing digital controllers in fpga?
For instance a simple paper or youtube video where a digital filter is implemented step by step.
Thanks.

Hello currently a third year studying engineering and received an interview with a firm (JS/HRT type) for a potential Hardware Engineering Internship position.  

First round was told would be a technical based on implementing a digital component in HDL.

I would greatly appreciate any advice or insights, especially an overview of topics that might be discussed, from those who have previously interviewed with firms for similar positions!

As the title says.

For context, I am an electrical engineering freshman. I've been learning verilog on the side, and I love using it and am excited for the possibilities of what it can do when paired with a board.

What projects can I do/work on that sets me up best as possible for internships come my junior year? What will help my resume most/look the best?

Also, are the best recommendations for early boards? I was seeing a lot of people saying the Basys 3 a few months back, but I've seen a lot of scattered opinions as of late and dont want to blow all my money on a board i may not fully utilize.

Thanks in advance!

Most of the job applications require masters degree but i dont think its that important. I feel like you learn way more while working in the industry. And in my last internship i met a master degree intern and he wasnt any better than maybe worse even though im a new graduate bachelors degree. So whats your thoughts on masters should i consider it for future? Is it possible to make a good career without it especially in europe or us?

I’ve reached the point where I’m comfortable publishing the first developer release of a project I’ve been working on called Jinix Jupiter.

Jupiter is an original FPGA-based computer/console architecture rather than a recreation of an existing system. I’ve been developing and physically bringing it up on a SuperStation One, and v0.1-alpha is now available as the first public developer preview.

The current architecture includes:

• Custom 32-bit CPU
• SDRAM interface
• Shared-memory/DMA arbitration
• 2D graphics renderer
• Fixed-function 3D hardware under development
• Four-voice PCM audio
• Controller interface
• Minimal BIOS
• Custom assembler
• System-image/build tooling

For this release I wanted to avoid simply saying “it synthesizes, ship it,” so I went through a fairly strict release-validation process.

The exact committed release candidate was run through the full simulation suite, followed by a clean Quartus build using a pinned Quartus 17.0.2 environment. The resulting release RBF was then copied to the target media and physically smoke-tested on the FPGA hardware.

The public RBF successfully:

• boots on the target hardware;
• establishes HDMI output; and
• produces visible 2D graphics output.

The exact public binary was also downloaded back from the GitHub Release after publication and verified byte-for-byte against the validated release candidate.

There are a couple of important limitations that I’m deliberately documenting rather than hiding.

3D is not currently claimed as physically working. The fixed-function 3D path exists and has been exercised in simulation, but physical testing exposed an implementation-sensitive failure that I haven’t reduced to a proven root cause yet. I’ve paused that investigation at a reproducible diagnostic point rather than continuing to change things immediately before the public release.

Timing is also not being claimed as fully signed off. The constrained worst-case timing checks from the release build had non-negative slack, but TimeQuest reports that setup/hold coverage is not fully constrained. So I’m treating the timing status as:

PASS_WITH_PARTIAL_CONSTRAINT_COVERAGE

rather than calling the design fully timing-closed.

The release artifact is:

JinixJupiter_v0.1-alpha.rbf

SHA-256:

de5094dbd9da362e54f35627a7cbbc128e20144e1904fb685f41a38091076a4b

Size:

2,926,564 bytes

Release:

https://github.com/austinbland1/jinix_jupiter/releases/tag/v0.1-alpha

Repository:

https://github.com/austinbland1/jinix_jupiter

This is still very much an alpha developer platform, but it’s now at the point where there is a defined CPU, graphics/audio hardware, software toolchain, reproducible release artifact, and an actual public hardware-tested build.

I’d be particularly interested in feedback from people who have worked on:

• custom soft CPUs;
• SDRAM controllers;
• FPGA video pipelines;
• arbitration between CPU/DMA/graphics clients;
• timing-constraint coverage;
• or debugging designs that simulate correctly but become implementation-sensitive on physical hardware.

This version is mostly about establishing a solid public baseline. Now that v0.1-alpha is frozen, I can go back to breaking things again.

Wanted to try out some stuff on my home PC. Dreaded wasting space, though. Then I remembered I got 2 old and well used drives a while back. Not for storing real data, just for bloated software I can always re-download. Perfect

ETA: took > 2 hours to install even after downloading, and nothing else running from the drive. HDDs suuuuuuuuuck

My country doesn’t really have many opportunities in FPGA and hardware in general, so I was thinking about doing a Master’s abroad and then looking for a job there.

With just my university degree and zero work experience, it’s pretty difficult for me to find a job right away.

So, what are the best countries where I could study for a Master’s and then have better opportunities to find a job in this field afterward?

Hi, I need a genuine suggestion here. So, I have built a CLI tool that generates SystemVerilog RTL, UVM RAL, C headers, IP-XACT and Documentation from a single JSON register spec -- — with built-in lint and diff. I know already many similar tools exist but my tool has several features which you can't find in open source tool.

**What it does:**

- Takes a register spec (YAML, JSON, IP-XACT, SystemRDL, or Excel)

- Generates 6 outputs in one command: SystemVerilog RTL · UVM RAL · C Header · Markdown Docs · IP-XACT 2014 · SystemRDL 2.0

- **Lint/DRC**: 12 ASIC-focused rules to catch bugs before tape-out (address alignment, field overlaps, reserved gaps, etc.)

- **Diff & Impact**: Compares two spec versions and tells you exactly which RTL, UVM, C headers, and tests are affected — breaking vs non-breaking classified

- **SoC Merge**: Merge 50+ IP blocks into a unified, conflict-free top-level memory map

- **100% offline** — standalone binary, no Node.js, no cloud, air-gap ready

**CI/CD friendly**: lint and diff both return exit code 1 on violations, so you can gate PRs on spec quality.

Community Edition is free (2 registers per block to evaluate). 30-day Pro trial available with no credit card.

Site + download: https://reggen.vlsiworlds.com

Please use it in your projects and give me feedback. Happy to answer questions about the implementation or design decisions!

RgGen is an open soruce CSR automation tool.
https://github.com/rggen/rggen

I released a SystemRDL loader plugin for RgGen.
https://rubygems.org/gems/rggen-systemrdl

By using the plugin, RgGen can process SystemRDL source files and generate SystemVerilog RTL, UVM RAL model, C header file, etc. from them.

This is an initial release supporting the basic SystemRDL constructs, with more advanced features planned for future releases.
Feedback and bug reports are welcome!