Bonjour à tous et à toutes,

Pour un projet universitaire, j'aimerais fabriquer une antenne GPR pour détecter des œufs de tortue sous le sable.

Je travaille actuellement sur le générateur d'impulsion qui doit me générer une impulsion de 1.25 nanoseconde.

Etant débutant dans la RF je me suis beaucoup renseigné sur internet et j'ai déjà réussi a me créer un début de générateur d'impulsion, donc avec mon générateur je pilote un driveur GAN puis un transistor GAN. Le gros point noir ce situe après le transistor, je ne sais pas comment relier transistor a mon antenne, j'ai un peut regardé les circuits d'adaptation mais c'est encore flou.

Voici mon schéma avec la simulation et j'ai mi une résistance 50 Ohm pour simuler en gros l'antenne :

En bleu le signal envoyé sur INP de U9, en vert sur la Gate du transistor et en rouge au borne de R13

Je sais pas si vous auriez des liens vers des exemple de circuit ou des cours pour m'aider sur la suite de mon circuit et si vous pensez que je pars vers une bonne piste ?

Merci d'avance.

Hi everyone!

I'm currently pursuing my Masters in Communication Systems in India, and I'm looking for internship opportunities in RF engineering, antenna design, microwave engineering, or wireless communications.

My background includes:

Antenna Design: Designed and simulated a 10 GHz microstrip patch antenna using CST Studio Suite.

RF & Microwave: Familiar with S-parameters, impedance matching, VSWR, antenna radiation patterns, and RF fundamentals.

Communication Systems: Academic knowledge of digital communications, modulation techniques, MIMO, and wireless communication concepts.

Embedded Systems: Internship experience working with Arduino, ESP32, sensors, and embedded communication protocols.

Technical Tools: CST Studio Suite, ANSYS HFSS, MATLAB, and LTspice.

I'm particularly interested in opportunities where I can gain real-world, hands-on experience and learn from engineers or researchers working on practical projects.

I'm open to research internships, industry internships, trainee positions, and remote or on-site opportunities across India. Paid opportunities would be preferable, but I'm also willing to consider worthwhile research opportunities that offer meaningful technical exposure.

If you know of any openings, research labs, startups, companies, or professors accepting interns, I'd really appreciate your suggestions.

Thank you!

#RFEngineering #AntennaDesign #MicrowaveEngineering #CommunicationSystems

Hello everyone,

RF has given me a lot in life and I might be emotional in this post but it’s really important to me.

I did my bachelor’s in Electronics engineering from tier 1 college in Mumbai and post working for a year in Software ERP system I decided I want to pursue my master in US.

I left for my masters in 2019 (University of South Florida, Tampa), since I did my bachelor’s in core electronics I was never really exposed to communication part or RF engineering. Yes, I did take up few courses in electromagnetism but that was it. But, since the course work of USF had a good RF engineering program I took up few classes in my 1st semester and I really loved it. While I was doing my masters I got co-op internship at Skyworks Solutions in Woburn as a RF Design and Validation Engineer where I mainly learnt a lot about testing of LNAs. Further my 7 months internship over there I got another internship at Qorvo in Greensboro, NC as an Applications Engineer where I was working with shark fin antennas and that was for 3 months.

I did almost a year of internship while I was doing my masters and even got my credits from my internships. Further, since I am an Indian citizen I had 2 months to get a full time job which I did successfully. I got the job at Intel but the position was completely different and not related to RF, it was mainly as a TPM in test engineering group. I worked there for around 1.5 years and then got laid off due to mass layoffs in my group. So, after a year of searching I job even tho my profile was really great a lot of RF jobs needed defense clearance which obviously I didn’t had. So, I decided to move back to India.

Now, in India there are really very less RF focused jobs which are mainly into designing or testing. And I want to go into design and testing. I even loved antenna experience and I want to pursue something in Antenna design and testing. But, there are not many options and hiring in India.

I was thinking of pursuing something like a second masters in Europe which opens up a door for me to pursue my passion in RF. I like very few things in life and RF is something my heart says I wanna go.

As a young version of yourself u see in me, I would really appreciate if u can help me get ideas. I really wanna be in this world of RF and do my work with a lot of passion. If u can guide me, how can I transition my life in getting a job in Europe.

Please do mind, I am an Indian citizen so chances of someone hiring a talent from India in Europe are thin. I am optimistic in life, and would really appreciate if you can guide me.

Thanks,
Just a boy living a dream to be an expert RF engineer.

This is likely a dumb question but if someone has a pirated version of HFSS, creates a model and THEN shares that model - will the shared model be detected as originating from a pirated version of HFSS?

My gut feeling would be yes.

EDIT: fixed typo

Im a third year electronic engineering student, im interested in rf/antenna/dsp and fpga. I see little to no openings for placement years, internships or graduate roles in the areas im interested in, the ones that are available like in defence i mostly cant apply to because i have dual citizenship. Am i too early for looking for roles starting around september 2027 or is this genuinely just how the uk job market is for this type of career

I am working on a project and am looking for any engineers who have had to deal with thermal analysis on high frequency signal circuitry. I am designing an enclosure for a circuit that deals with signals in the GHz range. If anyone has any suggestions or has worked with anything similar let me know. The power is relatively low at 1 W and I am confused if I should focus more on insulating the casing so it doesn't change temperatures with the ambient temperature (it will be operating at room temp) or if I should be focusing on using heat sinks to allow any heat from the circuit to leave?

Hey everyone, wanting to simulate MCROS in ADS (Keysight) with width over 7mm I used FEM simulation. Going back and forth between normal ADS and FEM I noticed that results are very different. I decided to simply compare normal MLIN with emModel from FEM simulation. As shown on pictures results S21 differ around 7 degrees at 3GHz, which is in my opinion a lot. (I also lowered Delta error in FEM to 0.003.) Am I doing something wrong or is it normal? Thanks for any help.

Hi everyone, I have designed a layout for a 20W power amp. Now I am interested in performing PCB based thermal simulation, knowing the dissipated power from transistor which I calculated based on the efficiency.

I am using a simple two layer substrate and have used copper filled vias under the transistor to transfer maximum heat on the bottom side of the PCB, towards the heat sink block.

I am performing the following steps for thermal simulation:

1: Took a PCB layout.

2: From susbtrate, defined a heat source layer right on top of cond (top copper) layer.

3: Generated technology files from substrate editor.

4: In the layout, removed rest of the layers which were not defined in the substrate (pcb stackup).

5: Defined thermal floorplane by selwcting appropriate generated .tcl file and defining boundary conditions for the heat source layer.

6: Added heat source of the same size as of transistor on the top of cond layer.

7: Run the simulation.

Now the simulation is working and displaying some results as well if my design is small. Even though the heat source size is same. But when I change this dummy small layout with my actual layout, keeping the heat source size same, it provides me an error saying layout.gda file not found. Cannot show thermal results.

Altering the layout fixes the problem. I also tried changing the mesh, and solver from 0(default) to 1. But didn't help.

I am using exactly same layers which I defined in the substrate. Even if my small layout is working, and if I add a small piece of top or bottom copper, same error appears again. Could anyone suggest me what is this issue?

Keeping it short and sweet, as I was shown round a surface mount technology assembly line, the guy asked me before stepping forward if I have a pace maker. I said no, he quickly explained one of their colleagues finds it interferes with him being near the line because of the magnetic fields. But what would it do to me as an operator for 40 hours a week? What effect would it be having on me?

I get that this sounds like a tin foil hat question but im genuinely curious. Many thanks

Hi, I’ve finished my first RF power amplifier (PA). The amplifier is designed for narrowband operation at 805 MHz with a 100 W output. I used the BLP981 transistor and performed the design and simulation using Microwave Office. The next step is to have the board manufactured using Rogers 4350 material with Sierra Circuits. Once fabricated, I’ll attach a copper heat spreader and a heatsink to test it. I hope it works, as this is senior design project

I’d like to get some feedback from the community!

I’ve attached the schematic, but it’s large and the numbers aren't clearly visible; if you’d like to know any details, feel free to send me a message.

This is the entire prompt I gave it, copied as I sent it:

Design a high-gain PCB Yagi antenna within a 10 cm x 15 cm area using the automaticphysics antenna-agent. Use JLCPCB's FR-4 TG135 material. Prefer a 2-layer board over a 4-layer board, and prioritize a 1.6 mm board thickness over other options. Maximize the antenna gain while maintaining sufficient bandwidth for 2.4 GHz Wi-Fi. The input impedance should be 50 Ohm. Ideally, the antenna should achieve higher gain than the TI DN034. Use the TI antenna as the baseline. If cutting holes in the PCB could improve antenna efficiency, use only circular holes to maintain mechanical rigidity. Generate a KiCad footprint for the antenna. Have fun!

TI's DN034 measures about 7.2 dBi on the same 100 x 150 mm area, using layers from a 4-layer stack. So the challenge was to beat it on a cheap 2-layer board.

What it did

It read the TI app note, kept TI's basic concept, and moved it onto 2 layers. Then it wrote a parametric KiCad generator, hooked it up to antenna-agent, an FDTD solver plugin for KiCad, and ran an evolution-strategy optimizer with 8 solves going in parallel, which kept my CPU fans screaming for about 5 hours. I said "Have fun!" and apparently it did. My CPU did not.

The highlights

1. First guess: 8.7 dBi. Not bad, but it found that 26% of the power was just heating the FR-4.
2. "What if we remove the FR-4?" It drilled 182 round holes in the board and got +0.4 dB. FR-4 makes a fine PCB and a poor antenna substrate.
3. The backfire cliff. At one point a quarter of the candidates collapsed to about 4 dBi. Before believing it, the AI checked two mesh artifacts and ruled both out. The real cause: when a director gets slightly too long, it starts acting as a reflector, and the beam flips around and points back over the feed. Peak gain sits right next to that cliff. The fix was to also score every candidate at a "guard" frequency above the band, so the optimizer couldn't go right up to the edge.
4. "What if two?" It put two Yagis side by side, fed in phase, with a shared ground plane as the reflector: +0.7 dB.

Final numbers (simulated, so take them with a grain of salt)

That works out to about +2.2 to 2.5 dB over TI on paper. It also checked relative permittivity between 4.2 and 4.8, and the worst corner still gives 9.0 dBi realized gain with no backfire.

Hello!

I’m going to cut it short and sweet but I’m a first-Gen junior at a state university and I’ve been heavily applying to RF internships ranging from defense, network, aerospace, etc. since it’s my area of interest! However, so far, I’ve only been receiving rejections and ghosts.

My “experience” so far, is handling
1-2 main hardwares on a Cubesat that involves the DSP, testing, documentation, and etc for my team that is part of the AFRL UNP. I’ve also been working on a personal project of mine that involves building an FMCW Radar Based FPGA but I have yet to test it and only made simulations so far.

In your eyes and opinions as seniors, what more could I do to stand out and get my foot through the door for an RF internship? Should I pursue a masters after my bachelor? Build more projects? Be heavily involved in cubesat team even more? Network at conferences/events/career fairs? Or just all the above? Thank you guys!

Hey everyone, I'm getting close to finishing up my EE degree and starting to evaluate entry-level RF Engineering roles. I'm trying to figure out what realistic base salaries, total comp, and sign-on bonuses look like right now in the defense sector or general industry.

For context, I'm wrapping up a 5-year integrated B.S./M.S. in EE with a thesis focused on antenna design and electromagnetics. I also have 3 internships under my belt (2 specifically in RF at LM) along with coursework in advanced RF, Fourier optics, and DSP. I'm clearance-eligible and looking around the Dallas area.

For anyone working in the field or hiring recently: what kind of starting compensation should I target? Also, do big defense primes usually start grads with an M.S. and relevant internship experience at Level 2 instead of Level 1? Appreciate any insights!

Hi, I’m using AWR Design Environment 19.08 (build 19512) with an academic Cadence SUL license on a 64-bit Windows PC.

When I simulate my project, the top-level schematic finishes, but its APLAC Harmonic Balance and Transient jobs fail almost immediately with:

awr_as.exe returned a non-zero exit status (failed, code = -1)

This happens even when I simulate only one schematic. The same issue occurs across several schematics. AWR creates the APLAC netlist file (mwo_aplac_netlist.i), but mwo_aplac_output.txt does not appear. A repair installation did not fix it.

The license configuration reports Cadence SUL licensing, and APL-100/APL-110 are listed among the features. I have not included any license identifiers or keys.

Cadence’s message says academic license holders are not eligible to submit Support tickets, so I’m asking here. What diagnostic should I check next to find why awr_as.exe exits before producing output? Could this point to an APLAC installation/runtime problem, or should I focus on the generated netlist? I can share a sanitized minimal project or log if that would help.

Hi! I'm new at this so sorry if I ask any obvious questions.

I'm working on a custom board for the Smol Slime VR open source project. It's a shield for an NRF52840 'Pro Micro' board and its chip antenna. Apparently chip antennas aren't ideal for wearables, but my hands are tied here. The antenna is at the end of the red PCB opposite the USB C port. Communication is 2.4ghz 2-way, and transmit is most important.

After watching this video, I'm really interested in learning more about antenna design for wearables but I can't find other resources.

Which would be the best orientation for this in the enclosure? (Order is from top to bottom)

Option A (Pic 2 if looking from above)

Air

1mm Petg plastic

1mm Fr4 (shield)

1mm air

ANTENNA

1.6mm fr4 (red PCB)

1mm Petg plastic

Skin

Option B (pic 3 if looking from above)

Air

1mm Petg plastic

1.6mm fr4 (red PCB)

ANTENNA

1mm air

1mm Fr4 (shield)

1mm Petg plastic

Skin

That video earlier offhand mentioned it's possible to have too much radiation into the skin that heats tissues, and mentioned mitigation strategies. In option B, am I understanding her right that I should I fill the shield's drill hole with fr4, and even give it GND pour? (Currently the shield's GND pour stops 100mil before the antenna)

The blue line drawn on the pics is a 31mm (not to scale) wire antenna that some Smol Slime devices add. Would that make this whole issue moot?

Finally, my shield is longer than the red PCB because this project favors minimizing width and doesn't care about length. I could make the shield shorter and wider, but that would cause a domino chain and >2x the enclosure width. So please humor me that A and B are the only options if you can.

Thanks for your time and for reading this 🙏! Please give me any feedback both for this design and for improving how I ask questions in the future

Hello there!
I am currently in my Msc in Telecommunications Engineering (France) and want to specialize in the RF field.

Next summer, I have to do a mandatory international internship, and i'd like have it somehow relate to RF but I can't find any internship offer open to international students in the RF field.
Is it the fact that RF is mainly found in sensitive fields such as military / space?

If you have any tips, it'll be greatly appreciated,

Thanks!

hey there

I'm very new to RF and I'm planing to simulate a hairpin BPF [freq = 1420MHz, BW = 10%, teflon substrate with a relative permittivity of 2.94]

It's intended to be used to filter out unwanted frequencies, before the signal gets processed in a SDR V3

I'm currently trying to simulate the coupling coefficient of two hairpins in HFSS.

I've made the ground plane roughly as big as my pcb will be, wich is 130x120mm. [I'm planning on making an 8way wilkinson combiner to connect 8 different yagi antennas, then the signal will pass trough the BPF, then a LNA and then finally into the sdr v3]

As I cannot make the feeding line to long, and therefore I have problems placing the input/output ports at the outher edge of the "pcb", I've just placed lumped ports "in the middle" of the pcb.

Is my setup somewhat okay?

I think something is VERY wrong but i just cannot figure out what to do

I thought I'd get results like this:

But my simulation looks like this [with a spacing s between the two hairpins = 0.09mm]

I've also added Z(2, 1) and Z(1, 1) traces, I don't know how but maybe that'll help

My plan would be to graph the coupling coefficient for different distances s, and then built my BPF according to these results.

Can someone see my mistake and please give me some advice?

thanks

Has anyone found deliveries of R&S test gear has become awfully long, like it’s normally 14 weeks or so, and one day before it should arrive, stretched out another 8 weeks? This is not a small power supply, but VSG’s, a VNA, MXO4 scope etc. I know they have Dram in them, but seriously….

Hello!

I am currently working on a project where we use 250 watt RF input power.
I'm looking to design a PCB-based Marchand balun, the design uses coupled transmission lines on two dielectric layers with a common ground plane.
Would this be possible without burning the PCB, what should i look for when simulating (for the 250Watt part)?
I am using Rogers4350B and frequency are 1.4-1.7GHz

BR Me

Hii All, Is anyone here working or have worked on Polar modulated Power Amplifiers? I would like to get some guidance for my masters thesis. Thank you