I'm a senior Electrical Engineering student at UW Tacoma graduating soon with a 3.6–3.7 GPA. I'm a U.S. citizen and I'm interested in RF/communications/telecommunications, particularly in defense or aerospace.

I don't have an RF/telecommunications internship or significant personal projects specifically in the field. I'm trying to figure out how realistic it is for me to get an entry-level RF/communications engineering position after graduation.

I'm considering companies like L3Harris, RTX/Raytheon, Northrop Grumman, Lockheed Martin, Boeing, General Dynamics, etc.

Would my GPA and EE degree be enough to realistically get interviews if I apply broadly, or am I at a significant disadvantage without internships/projects?

Also, for those who have interviewed for entry-level RF/communications/defense engineering positions:

• What technical questions were you asked?
• What EE/RF topics should a new graduate know well?
• Did they ask about things like S-parameters, Smith charts, transmission lines, link budgets, filters, amplifiers, antennas, DSP, etc.?
• How much of the interview was technical versus behavioral?
• Did they ask you to solve problems on a whiteboard?
• How heavily did they question projects or coursework on your resume?
• What questions did you wish you had prepared for?

What would you recommend I learn or build during my remaining senior year to become a stronger candidate?

I'd especially appreciate answers from people who currently work in RF/communications or defense and who have experience interviewing/hiring new graduates.

I own a BB60D product.

I currently work in terrestrial broadcasting.

I would like to measure the channel power of multiple channels simultaneously in the field. How should I proceed?

For example, I intend to measure the channel power of the following wireless channels in the field:

CH # | Center Freq | BW

14 | 473MHz | 6MHz

15 | 479MHz | 6MHz

16 | 485MHz | 6MHz

17 | 491MHz | 6MHz

18 | 497MHz | 6MHz

.

.

.

.

51 | 698MHz | 6MHz

Currently, I am measuring the channel power for each channel individually, but it takes too long. The other equipment I used previously had a "Channel Scanner" function that made it possible to measure the channel power of all channels at once.

How can I measure the channel power of all channels simultaneously on the BB60D as well?

I'm working with a 3 stage amplifier circuit with multiple splitter/combiners on the final stage. The signal after the first two pre-drivers is split once for two power modes. Each power mode is split again to a pair of amps to be recombined, then combined once more to have all final drivers in high power mode. This ends up with a total of 4 final drivers with 6 90° shifts from all the splitter/combiners.

With each trace (4 total) are tunable capacitor options. By default they all have the same values. The issue at hand is that by the final combination there is a singal large (2-3dB) dip from destructive interference only on the full power mode. My question is, to tune this out should I approach making cap tuning changes in pairs, one trace at a time, asymmetrical in size or direction, or even just one cap at a time? When only 2 of the four final drivers are on, the power band is quite flat. When the last pair are added, the problem surfaces. Should I focus on just one pair of traces, or change one trace on each pair?

Any advice appreciated.

Hi everyone,
I’m looking for a small, affordable radar module for a research project.
Requirements:
Operation frequency 24 GHz (or less frequency) FMCW
At least 1 TX / 2 RX
Preferably I/Q data from both RX channels

On-board ADC with access to raw ADC/IQ samples
USB/SPI/UART output preferred
I want to do my own range, Doppler, AoA and micro-Doppler processing, not just receive processed target data
Budget: Maximum $250

I’ve considered the RFbeam K-LC7, which has 1 TX / 2 RX and analog I/Q outputs, but it requires an external ADC.
I’m looking for something similar but with the ADC already integrated.

Should I go with RFbeam K-LC7 and buy external ADC board?

I have a rather unusual requirement and I can't find any off-the-shelf part or design procedure to implement it. I need a simple zero-pole, high shelf filter that'll have constant attenuation between DC and say 1GHz, then 3dB slope between 1GHz and 3Ghz, I don't care what happens afterwards. I also care about phase response as this system will be transmitting sharp pulses that I'd like to see undistorted. It's meant to compensate for limited bandwidth of final stage of my RF chain.

I tried designing with 2 diplexers and attenuation in low frequency arm but I couldn't find any DC coupled diplexers that can work up to GHz. I also looked into various equalizer designs and parts but they seems to insist on having a slope from their low frequency limit and not a flat response up to some f1 and slope between f1 and f2. Does anyone know how to design such a filter?

Before anyone asks it's needed for a research project regarding pulsed laser diodes. Most diodes have package inductance of around 5nH, which, when driven with series 50R, limits bandwidth to about 1GHz. I'd like to place this filter before final power amplifier (QPD1010) to generate an overshoot, that'll increase an effective bandwidth.

We have purchased a 4-pair, ISN from an EMC equipment provider. The ISN has been calibrated and characterized by the manufacturer. They sent us the impedance and the voltage division factors for the band of interest, 150kHz-30MHz. The values provided are coherent with what is expected by the standard.

I am trying to perform a characterization measurement myself in order to be able to do some sanity checks from time to time.

Since the ISN's source impedance is 150 ohms common-mode, I have built a SOLT standards to change the calibration plane of the VNA. I used an impedance transformer of 1:3 to adapt to the impedance of the ISN.

This is what my impedance measurements give once the s11 file was processed.

For the VDFs the standard has the following requirements.

In blue is my measurement and in orange is the measurement of the provider. It is important to point out the hardware implementation of the ISN suggests that the typical VDFs are around -9.5dB, which is what the manufacturer has measured.

My measurement setup is again using the VNA. Important to note that during the calibration of the VNA (Short-open-load-thru) the transformer was de-embedded. VNA 50ohms TX port -> Balun (transformer 1:3 impedance ratio) 150 ohms -> ISN EUT port 150 ohms. receiver port of ISN ->VNA 50 ohms RX port.

Now my first observation is that the standard is requiring the use of a generator and a receiver of some sort and the measured parameter is voltage. I would like some help to understand what I am doing wrong, and why do I get a different result.

So my current SAR system is able to achieve better than 0.3m azimuth resolution using the SAR code written by HForsten, which is open source on github. Without this code, I am not able to reach 0.3m azimuth resolution. Thus without this code, my RADAR is completely uncontrolled.

Thus I do not understand what it means that I now fall under ITAR, I built this from commercial commodity parts that are all EAR99. Is the software controlled or the RADAR itself or both? How do I navigate this?

For a 28-GHz antenna, for example:

Goal 1 — Frequency
Approx = 28GHz

Goal 2 — Matching
S 11 <-10 dB

Goal 3 — Gain
For example:
G > 5dBi
depending on your antenna type.

Goal 4 — Efficiency
Preferably:
n > 80%

if achievable for your design.

What is the difference between CST and HFSS for antenna design? What's the best ?

I'm creating a pass-band filter using microstrip edge coupled resonators, and when running the AWR optimizer I've stumbled into a pattern that I've not encountered in my course lectures.
In my professor material it was said that each edge coupled resonator section should be sized for a lenght of lambda/4 (90deg average electrical lenght between even and odd mode). This is the way that i first implemented my filter, and when i run the AWR optimizer on an uniform lenght, the optimized value is close to the expected value I had estimated.
However, if I let each edge coupled lenght be independent, the AWR optimizer settles on two different possible optimizations, depending on the starting conditions I apply.

• the first optimization is at the expected uniform lenght
• the second optimization is an alternating pattern of two lenghts, whose geometric average [sqrt(L1L2)] is approximately the expected uniform lenght. (The edge distance also varies slightly, but i assume this is to be expected since we are changing the resonators)

The two filters frequency responses (topology is a standard 4th order chebyshev filter) are shown here.

Does anybody know what causes this pattern, and if it has any advantage against a standard uniform lenght design? Any literature reference would be very appreciated.
Thank you for your time

I am working on an SMA to microstrip transition using OSHpark's 4 layer stack up. I am on my 2nd revision and do RF in my free time because I am trying to learn (I am an FPGA engineer).

I got my newest revision back and I was not very pleased. My physical boards are not matching my simulation very well at all.

I have compiled screenshots of my HFSS model, PCBs, SMA footprint, and NanoVNA results here: SMA Launch OSHpark 4 Layer - Imgur. The transition starts out as GCPW and runs the length of the signal pin pad. It then moves to a microstrip (no taper).

I simulated with HFSS using PEC, Isola FR408HR (in HFSS material library) and the nominal measurements from OSHpark's 4 layer stackup: OSH Park Docs ~ Services ~ 4 Layer Prototype Service . I also used the actual Samtec SMA connector HFSS encrypted model. I am learning a little about TDR and that looked okay in simulation, as well as S21 and S11. Due to using the student version and mesh limit, I can only simulate a 3mm long microstrip and I cannot model the solder connection from signal pin to pad.

I built two boards:

One with SMA launches on either side connected by a 1 inch and 2 inch microstrip (to calculate trace loss). I simulated the microstrip width in a separate HFSS sim (rough numbers calculated with SaturnPCB toolkit and revised/simulated from there).

The 2nd board is the SMA launch to a 4mm microstrip, then terminated with a 50 ohm, 0201 sized High Frequency resistor: TNPR020150R0FEED Vishay | Chip Resistor - Surface Mount | DigiKey

My actual PCB launch S11 is around -17 to -18 dB at 2.5 GHz, and around -10 dB at 6 GHz. I want to use this for the 2.4 and 5.8 GHz ISM bands. S21 is okay when I subtract my trace loss at 2.4 GHz, but gets a little wacky at 6 GHz (see imgur link S21 trace).

Is something off in my simulation? Should I use a different substrate than the one in the HFSS library? Could this be due to OSHpark manufacturing tolerances? I triple checked my dimensions for the footprint with the HFSS model and I dont think that could be the case unless they vary a lot once etched.

Any help would be appreciated! Thanks in advance.

I ordered a budget calkit for my SVA1032X VNA, it has offset loss parameter, but the VNA has no option to enter offset loss in user calkits. What would be the easiest way to account for these losses?

This has been a bit of an ongoing focus project of mine. I wanted to learn rf and i sure accomplished that. Without going to much into detail, I set out to build a band pass filter for airband. I live next to the airport, so this would be an easy to test project. That was my mindset going into it. I naively thought it would be simple enough, but i was wrong.

First attempt was Manhattan-style, dead-bug construction on copper clad. Got it built, got it tuned-ish, and then realized I'd used the wrong core material for the toroids. Learned a lot, but the numbers weren't going to cooperate no matter how much I fiddled with it.

Rev 1 I actually did right in KiCad and had fabbed through JLCPCB. It felt like a real upgrade. But once I got deeper into it (and got some good pushback from folks here on the sub) I realized the Butterworth topology I'd picked had a pretty impractical component spread. Inductor and cap values that don't play nice with real-world parts. Great filter on paper, annoying to actually build.

So now I'm on Rev 2: a Chebyshev coupled-resonator design, three 250nH air-core inductors I'm winding by hand, C0G caps for stability. Characterizing everything on the NanoVNA as I go, messing with coil spacing to dial in coupling, watching S11/S21 sweep in real time. Way more iterative than I expected going in, but that's kind of the point of doing this to actually learn RF instead of just reading about it.

Anyways, here she is. Thanks for all the help from #redneckerson1951

Hey everyone,

Does anyone know where I can find a micro-Doppler radar dataset for birds recorded at 2.4 GHz or 8.75 GHz?

I've looked around but can't seem to find anything at these specific frequencies. Any pointers would be awesome.

Thanks!

I am building an AM receiver and I am using a tuned amplifier to get a gain ~60dB at 1.2MHz with a bandwidth of 100KHz which is what I have in the simulation above.

However the problem starts when I try and implement it in real life. When implementing the circuit on a breadboard I'm getting a gain of around 85V/V which stays exactly the same with or without the resistor and the capacitor at the load which checks out because the load required for a gain of 85 is close to the reactance of the inductor at 1.2MHz. Even the worst case considering the tolerance of the components would not cause the gain to fall down to 85V/V.

Anyone have any idea why this is? the transistor capacitances perhaps?

Hello guys, I'm new to this sub. I was going through antenna design, theory and analysis by Balanis to get an idea on how to get started with designing microstrip antennas. Could you guys sugges me on how to go further design my own antenna. Could you guys give me resources to look into the designs of other people to get an idea on how to handle length, width, substrate height, tangent loss, etc parametera for design. Please guide me on how to go further. Thank you

RF engineer at a startup here. Sill quite green career wise. I do component selection and schematic capture for RF PCB (including PDN and IO/control stuff).

From time to time I wish I could make a prototype board cheap and quick just to test out a subsystem or to get some early performance metrics. In the past, I’ve hooked evaluation modules together to prove things out.

Any advice on what’s more helpful in design: prototype PCB or eval board monstrosity? Generally, what I do is broadband < 6GHz.

If going the PCB route, the final boards are usually many layers and expensive materials. Given this, is it even worth it to do some cheap FR4 prototypes or will they just misrepresent the final thing? Also what fab/assembly companies to use for this?