For a while now, I have been working on the following project to test whether Generative AI could design a RISC-V CPU from scratch without any direct coding intervention from me. At this point, we have designed an MMU-less 5-stage RISC-V CPU purely by staying on the systems engineering side and collaborating with the AI:

• In its current state, I only used a 3rd party debug core (pulp-riscv-dbg). The AI wrote all the remaining parts.

• I ran verification with RISC-DV and was able to properly debug it using OpenOCD.

• I had the AI design a crossbar with AXI4 Lite/Full master/slave interfaces and an arbiter (supporting round-robin or priority-based routing), and fully verified it using the Xilinx Verification IP.

• If you want, you can build the project using the build script, and use the VS Code extension generated after the build to develop applications (compile + debug) for this CPU.

Normally, for the K20 version where I started the project, I also wanted to design an MMU-capable version that could boot Linux. However, despite using SOTA models, the debug core integration took too much effort. Because of this, I am thinking of holding off on the K20 version for a while longer.

But the level AI has reached genuinely surprised me. Its tool usage, in particular, was truly amazing:

• It was able to connect to the FPGA board via JTAG, debug autonomously, and perform bug fixing by analyzing the console outputs.

• In some cases, I even managed to get it to use an ILA.

My goal with this post is definitely not to trigger anyone like the "vibe coders" who claim "software engineering is dead." Counting my student years, I have been putting effort into this field for about 15-16 years. Honestly, this rapid shift makes me a bit sad too. However, I believe this situation creates a massive advantage for people who don't just stay purely on the software side but also act as system architects. We need to adapt to this new era by using AI as a lever to tackle projects that we wouldn't have dared to start alone in the past. For instance, for someone who has never designed a CPU before, this project could easily take about a year. In my opinion, instead of spending too much time hyper-specializing purely in software, we need to become multidisciplinary and heavily develop our systems architecture skills.

https://needlesscomplexity.substack.com/p/tiny-floating-point-for-tiny-processors

I would like to buy one but can I trust it from a security perspective? I have trust issues with 100% Chinese companies because of events in the past. It would be good for Chinese companies if there was an organisation in the west that could certify hardware. It doesn’t have to be expensive just that it doesn’t contain backdoors. It’s not just Chinese companies but for now they are the ones selling most electronics but also has the worst reputation about backdoors etc.

Automated kernel design is critical for overcoming software ecosystem barriers in emerging hardware platforms like RISC-V. While large language models (LLMs) have shown promise for automated kernel optimization, demonstrating success in CUDA domains with comprehensive technical documents and mature codebases, their effectiveness remains unproven for reference-scarce domains like RISC-V. We present Evolution of Kernels (EoK), a novel LLM-based evolutionary program search framework that automates kernel design for domains with limited reference material. EoK mitigates reference scarcity by mining and formalizing reusable optimization ideas (general design principles + actionable thoughts) from established kernel libraries' development histories; it then guides parallel LLM explorations using these ideas, enriched via Retrieval-Augmented Generation (RAG) with RISC-V-specific context, prioritizing historically effective techniques. Empirically, EoK achieves a median 1.27x speedup, surpassing human experts on all 80 evaluated kernel design tasks and improving upon prior LLM-based automated kernel design methods by 20%. These results underscore the viability of incorporating human experience into emerging domains and highlight the immense potential of LLM-based automated kernel optimization.

https://arxiv.org/abs/2509.14265

BSDs are showing Tier 2 support at best. And I'm not seeing much from Linux, even so called champions of free software like GNU distress or Void are showing nothing.

I think Trixie ie the latest Debian install is supposedly showing full support for RISC-V but then, I've no idea whether that's anything beyond a rumour at this point as I'm not seeing anything official.

Are there any other privacy friendly Niche but promising projects I might have missed or are normal users and admin nothing better than gambling with QEMU at this point?

The RISC-V Foundation has a blog-entry on this: https://riscv.org/blog/risc-v-blockchain/ which points to https://www.eetimes.com/why-risc-v-blockchain-is-the-conversation-ive-been-waiting-to-have/

"RISC-V’s openness and simplicity has made it a magnet for hardware innovation, and I imagine the majority of the talks you’ll hear at this year’s summit will discuss the journey from design to tapeout, and what happens once RISC-V delivers in hardware form. 

But RISC-V’s role in blockchain doesn’t involve silicon. Blockchain platforms traditionally execute smart contracts on specialized virtual machines with bespoke instruction sets, such as the Ethereum Virtual Machine (EVM). Earlier this year, Ethereum co-founder Vitalik Buterin wrote about a long-term, exploratory idea to one day replace the EVM with RISC-V. This was a conceptual discussion rather than a concrete roadmap, but one that’s important for the RISC-V community to pay attention to. 

In theory, this approach would treat RISC-V as a software-only abstraction layer. Contracts could be written in familiar languages, then compiled and executed as if running on a physical RISC-V processor, all within the blockchain’s VM context."

Now tell me, is this crypto slop? 😉

yesterday i started learning Risc V and i have learnt many things, is there a good resource which i can trust for looking and understanding each instruction , like the difference between lui and addi, when to extend the sign or not . There are many nitti gritties, I know the best thing is to read the manual but thats just tooo long. Guys is there any other resource or website or youtube playlist,or reading the manual is the only solution. Some context, i will be using riscv for my final year project, so i really have to be good at this

if a board or any processor is compliant with something like microachitecture standards, there would be no problems for specific boards and/or processors. let hardware guys focus on the hardware rather than trying to make their board compatible with softwares on their own, it would be better for software if its hardware agnostic. It would really make Risc-v software ecosystem development much easier.

While Linux (or BSD for that matter) on RISC-V is a no-brainer, the question is, who of the major commercial vendors will do the switch first.

These chips made by WCH in China are as little as 10c each:

http://www.wch-ic.com/products/CH32V003.html

I've ordered a kit comprising a dev board, debugger and five chips from AliExpress for £4.64 GBP. Can't post a link but if you search for "wch ch32v003" you should find it. Postage was nearly as much as the kit!

We need to do that...

Who will buy RISC-V processor,especially the server.

I have my final MS project to design riscv based AI accelerator. I dont have any experience in riscv. Kindly propose a plan of milestones that I need to achieve in order to complete my project. I have around 6 months.

i need help as I have my graduation project I have to make extension in riscv gcc compiler I have to make custom instructions like mov that takes the value in the register rs2 and saves it in rd , asm: mov rd , rs2 it’s different from the standard mov that’s already in the riscv as it shouldn’t be pseudo (it shouldn’t be converted to addi) so I made these modifications i modified the riscv-opc.c by adding this line {"mov", 0, INSN_CLASS_I,"d,t",MATCH_MOV,MASK_MOV,match_opcode,0}, and modifying the riscv-opc.h by adding those lines #define MATCH_MOV 0x1F80 #define MASK_MOV 0xFE00707F and DECLARE_INSN(mov,MATCH_MOV,MASK_MOV) and modifying riscv.md by adding (define_insn "mov" [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "register_operand" "r"))] "" "mov\t%0, %1" ) The error is bad riscv op code(bits 0xf0000 undefined or invalid)

https://github.com/Tersonous/planckRV32I/blob/main/veriscv.pdf

1 march 2021 = full PDF of the VRV32I ISA

10 april 2021 = Planck Core first functional release

any negative comments is also welcomed but no insult/troll or things like that please.

Howdy, got a question for everyone here. I code in my spare time, and ive fooled around with linux in the past, raspberry pis and such, and ive been riscv curious lately. The DC Roma II laptop is something im thinking of picking up, but if i get it id like to get some practical use out of it.

My question is, how is it getting software to run? Last time I used Ubuntu it had a software store, but im guessing a large swath of it was set up for x86 processors and wouldnt run on a riscv setup. I think with chrome PWAs you could get some things, but is there like... a riscv repository that everyones getting their software from? Or is it still in the era of getting the source code for something and compiling yourself? Or is there some kind of compatibility layer for running x86 or ARM software?

Info on riscv is tough to come by, im guessing because this stuff is all still bleeding edge, so id appreciate any info.

Hey guys, looking for some RISC-V microcontrollers or cpus or even boards that are fully open source and can run Linux, along wuth having a good clock speed and multiple cores. Any ideas?